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| munich256 multichannel network interface controller for hdlc/ppp peb 20256 e version 2.1 data sheet, ds2, april 2001 datacom never stop thinking.
edition 04.2001 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 4/9/01. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. datacom munich256 multichannel network interface controller for hdlc/ppp peb 20256 e version 2.1 data sheet, ds2, april 2001 never stop thinking. peb 20256 e pef 20256 e data sheet 4 04.2001 revision history: 04.2001 ds2 previous version: preliminary data sheet 11.1999 major changes to document since last version page description 25 pin diagram added 16-port mode 26 pin diagram added 28-port mode 54 remote payload loop block diagram redrawn 154 swap the bit positions of tbrtc and tbftc in the cspec_buffer register as their bit postitions were not correct in the preliminary data sheet. 155 swap the postions of tbrtc with tbftc in table 8-7, as their column positions were not correct in the preliminary data sheet 159 fixed typo in cspec_imask register, replaced rofd with rfod 190 fixed typo in iqmask, replaced rofd with rfod 203 update voltage min/max information for table 9-1 absolute maximum ratings 205 update timing information for table 9-4 dc characteristics (pci interface pins) 206 update timing information for table 9-5 pci clock characteristics 207 update timing information for table 9-6 pci interface signal characteristics 210 update timing information for table 9-8 intel bus interface timing 211 intel bus interface timing diagram modified. the setup and hold times for ?ld to lrdy? was not a valid timing parameter. instead, the setup and hold parameters for ?ld to lrd? were specified. 213 update timing information for table 9-9 intel bus interface timing (master mode) 213 timing parameter (setup time) 67a was changed from ?ld to ldry? to ?ld to lrd?, because it was not a valid timing parameter. 213 timing parameter (hold time) 67b was changed from ?ld to ldry? to ?ld to lrd?, because it was not a valid timing parameter. 215 update timing information for table 9-10 motorola bus interface timing 218 update timing information for table 9-11 motorola bus interface timing (master mode) peb 20256 e pef 20256 e data sheet 5 04.2001 for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 20256 e pef 20256 e data sheet 6 04.2001 preface the multichannel network interface controller for hdlc/ppp is a multichannel protocol controller for a wide area of telecommunication and data communication applications. organization of this document this data sheet is divided into ten chapters and is organized as follows: ? chapter 1 munich256 overview gives a general description of the product and its family, lists the key features, and presents some typical applications . ? chapter 2 pin description lists pin locations with associated signals, categorizes signals according to function, and describes signals. ? chapter 3 general overview this chapter provides short descriptions of all the internal functional blocks. ? chapter 4 functional description gives a detailed description of all functions ? chapter 5 interface description this chapter provides functional diagrams of all interfaces. ? chapter 6 channel programming / reprogramming concept this chapter provides a detailed description of the channel programming concept. ? chapter 7 reset and initialization procedure gives examples of the initialzation procedure and operation. ? chapter 8 register description gives a detailed description of all on-chip registers. ? chapter 9 electrical characteristics peb 20256 e pef 20256 e data sheet 7 04.2001 gives a detailed description of all electrical dc and ac characteristics, and provides timing diagrams for all interfaces. ? chapter 10 package outline . shows the mechanical values of the device package. peb 20256 e pef 20256 e data sheet 8 04.2001 peb 20256 e pef 20256 e table of contents page data sheet 9 04.2001 1 munich256 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3 general system integration munich256 . . . . . . . . . . . . . . . . . . . . . . . . . 23 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 pin diagram 16-port mode munich256 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 pin diagram 28-port mode munich256 . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.6 local microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.7 serial interface 16-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.8 serial interface 28-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.9 test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.10 power supply and no-connect pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3 internal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.1 port handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.1.1 selectable port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.1.2 external timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.1.3 local port loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1.4 remote payload loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.1.5 remote channel loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.1.6 test breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2 time slot handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.1 channelized modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.2 unchannelized mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3 data management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.1 descriptor concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3.2 receive descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.3.3 data management unit receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.4 transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.5 data management unit transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.6 byte swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.3.7 transmission bit/byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4.1 internal receive buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 peb 20256 e pef 20256 e table of contents page data sheet 10 04.2001 4.4.2 internal transmit buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5 protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5.1 hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5.2 bit synchronous ppp with hdlc framing structure . . . . . . . . . . . . . . 77 4.5.3 octet synchronous ppp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.4 transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.6 mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.7 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.7.1 layer two interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.7.1.1 general interrupt vector structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.7.1.2 system interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.7.1.3 port interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.7.1.4 channel interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.7.1.5 command interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.7.2 mailbox interrupts to the local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.1 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.1.1 pci read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.1.2 pci write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.2 spi interface (rom load unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.2.1 accesses to a spi eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2.2 spi read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2.3 spi write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3 local microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.1 intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.1.1 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.1.2 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.3.2 motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.3.2.1 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.3.2.2 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.4 serial line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.4.1 interface timing in 16-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.4.2 interface timing in 28-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.5 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6 channel programming / reprogramming concept . . . . . . . . . . . . . . 115 6.1 channel commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.2 transmit channel commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3 receive channel commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7 reset and initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.1 chip initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2 mode initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 peb 20256 e pef 20256 e table of contents page data sheet 11 04.2001 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.1.1 pci configuration register set (direct access) . . . . . . . . . . . . . . . . . 123 8.1.2 pci slave register set (direct access) . . . . . . . . . . . . . . . . . . . . . . . . 125 8.1.3 pci and local bus register set (direct access) . . . . . . . . . . . . . . . . . 127 8.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2.1 pci configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2.2 pci slave register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.2.3 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.3.1 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.3.2 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.3.3 transmit synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.3.4 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.3.5 receive synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.4 interface timing in 16-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.5 interface timing in 28-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.6 mailbox interrupts to the local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.7 selectable port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.8 external timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.9 local port loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.10 remote payload loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.11 remote channel loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.2.12 test breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.3 serial interface 16-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.4 serial interface 28-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.5 pin diagram 16-port mode munich256 . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.6 pin diagram 28-port mode munich256 . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.7 general system integration munich256 . . . . . . . . . . . . . . . . . . . . . . . . 161 8.8 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.8.1 pci and local bus slave register set . . . . . . . . . . . . . . . . . . . . . . . . 194 9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 9.1 important electrical requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 9.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 9.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 9.4.1 pci bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 9.4.2 spi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 9.4.3 local microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . 209 9.4.3.1 intel bus interface timing (slave mode) . . . . . . . . . . . . . . . . . . . . . 209 9.4.3.2 intel bus interface timing (master mode) . . . . . . . . . . . . . . . . . . . . 211 9.4.3.3 motorola bus interface timing (slave mode) . . . . . . . . . . . . . . . . . 214 9.4.3.4 motorola bus interface timing (master mode) . . . . . . . . . . . . . . . . 216 peb 20256 e pef 20256 e data sheet 12 04.2001 9.4.4 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 9.4.4.1 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 9.4.4.2 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 9.4.4.3 transmit synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . 222 9.4.4.4 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 9.4.4.5 receive synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 9.4.5 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 9.4.6 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 11 list of abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 peb 20256 e pef 20256 e list of figures page data sheet 13 04.2001 figure 1-1 munich256 16-port mode logic symbol . . . . . . . . . . . . . . . . . . . . . . 22 figure 1-2 munich256 28-port mode logic symbol . . . . . . . . . . . . . . . . . . . . . . 23 figure 1-3 system integration of the munich256 . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 2-1 munich256 pin configuration 16-port mode . . . . . . . . . . . . . . . . . . . 25 figure 2-2 munich256 pin configuration 28-port mode . . . . . . . . . . . . . . . . . . . 26 figure 3-1 munich256 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 4-1 port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 4-2 local port loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 4-3 remote payload loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 4-4 remote channel loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 4-5 test breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 4-6 time slot assignment in channelized modes . . . . . . . . . . . . . . . . . . . 58 figure 4-7 descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 4-8 receive buffer thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 4-9 transmit buffer thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 4-10 hdlc frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 4-11 bit synchronous ppp with hdlc framing structure . . . . . . . . . . . . . . 77 figure 4-12 mailbox structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 4-13 layer two interrupts (channel, command, port and system interrupts 81 figure 4-14 interrupt queue structure in system memory . . . . . . . . . . . . . . . . . . . 82 figure 4-15 mailbox interrupt notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 5-1 pci read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 5-2 pci write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 5-3 spi read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 5-4 spi write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 5-5 intel bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 5-6 intel bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 5-7 motorola bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 5-8 motorola bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 5-9 supported frame structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 5-10 t1 mode frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 5-11 e1, 4.096 mhz and 8.192 mhz interface timing in 16-port mode . . . 110 figure 5-12 unchannelized mode interface timing . . . . . . . . . . . . . . . . . . . . . . . 111 figure 5-13 t1-mode interface timing in 28-port mode . . . . . . . . . . . . . . . . . . . . 111 figure 5-14 e1-mode interface timing in 28-port mode . . . . . . . . . . . . . . . . . . . . 112 figure 5-15 block diagram of test access port and boundary scan unit . . . . . . 113 figure 8-1 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-2 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-3 transmit synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-4 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-5 receive synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-6 supported frame structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 peb 20256 e pef 20256 e list of figures page data sheet 14 04.2001 figure 8-7 t1 mode frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-8 e1, 4.096 mhz and 8.192 mhz interface timing in 16-port mode . . . 161 figure 8-9 unchannelized mode interface timing . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-10 t1-mode interface timing in 28-port mode . . . . . . . . . . . . . . . . . . . . 161 figure 8-11 e1-mode interface timing in 28-port mode . . . . . . . . . . . . . . . . . . . . 161 figure 8-12 mailbox interrupt notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-13 port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-14 local port loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-15 remote payload loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-16 remote channel loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-17 test breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-18 munich256 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-19 munich256 pin configuration 16-port mode . . . . . . . . . . . . . . . . . . 161 figure 8-20 munich256 pin configuration 28-port mode . . . . . . . . . . . . . . . . . . 161 figure 8-21 system integration of the munich256 . . . . . . . . . . . . . . . . . . . . . . . 161 figure 8-22 munich256 16-port mode logic symbol . . . . . . . . . . . . . . . . . . . . . 161 figure 8-23 munich256 28-port mode logic symbol . . . . . . . . . . . . . . . . . . . . . 161 figure 9-1 input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 9-2 pci clock cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 9-3 pci input timing measurement conditions . . . . . . . . . . . . . . . . . . . . 206 figure 9-4 pci output timing measurement conditions . . . . . . . . . . . . . . . . . . 207 figure 9-5 spi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 9-6 intel read cycle timing (slave mode) . . . . . . . . . . . . . . . . . . . . . . . 209 figure 9-7 intel write cycle timing (slave mode) . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 9-8 intel read cycle timing (master mode, lrdy controlled) . . . . . . . . 211 figure 9-9 intel write cycle timing (master mode, lrdy controlled) . . . . . . . . . 211 figure 9-10 intel read cycle timing (master mode, wait state controlled) . . . . . 212 figure 9-11 intel write cycle timing (master mode, wait state controlled) . . . . . 212 figure 9-12 intel bus arbitration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 9-13 motorola read cycle timing (slave mode) . . . . . . . . . . . . . . . . . . . . 214 figure 9-14 motorola write cycle timing (slave mode) . . . . . . . . . . . . . . . . . . . . 214 figure 9-15 motorola read cycle timing (master mode, ldtack controlled) . . . 216 figure 9-16 motorola write cycle timing (master mode, ldtack controlled) . . . 216 figure 9-17 motorola read cycle timing (master mode, wait state controlled) . . 217 figure 9-18 motorola write cycle timing (master mode, wait state controlled) . . 217 figure 9-19 motorola bus arbitration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 9-20 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 9-21 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 9-22 transmit synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 9-23 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 9-24 receive synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 figure 9-25 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 peb 20256 e pef 20256 e data sheet 15 04.2001 figure 9-26 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 peb 20256 e pef 20256 e data sheet 16 04.2001 peb 20256 e pef 20256 e list of tables page data sheet 17 04.2001 table 1-1 interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4-1 interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 4-2 receive descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 4-3 transmit descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 4-4 example for little/big endian with bno = 3 . . . . . . . . . . . . . . . . . . . . . 72 table 4-5 example for little big endian with bno = 7 . . . . . . . . . . . . . . . . . . . . . 72 table 4-6 interrupt vector structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 5-1 correspondence between pci memory space and chip select . . . . . 101 table 5-2 c/ be to la/ lbhe mapping in intel bus mode (8 bit port mode) . . . . 104 table 5-3 c/ be to la/ lbhe mapping in intel bus mode (16 bit port mode) . . . 104 table 5-4 c/ be to la/lsize0 mapping in motorola bus mode (8 bit port mode) 107 table 5-5 c/ be to la/lsize0 mapping in motorola bus mode (16 bit port mode) . . 107 table 6-1 channel specification registers and channel commands . . . . . . . . 115 table 8-1 pci configuration register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 8-2 pci slave register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 8-3 pci and local bus slave register set . . . . . . . . . . . . . . . . . . . . . . . 127 table 8-4 threshold codings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 8-5 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 8-6 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 8-7 transmit synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 8-8 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 8-9 receive synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 8-10 bit shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 8-11 interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 8-12 bit shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 9-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 9-2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 9-3 dc characteristics (non-pci interface pins) . . . . . . . . . . . . . . . . . . . 204 table 9-4 dc characteristics (pci interface pins) . . . . . . . . . . . . . . . . . . . . . . . 205 table 9-5 pci clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 9-6 pci interface signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 9-7 spi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 9-8 intel bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 9-9 intel bus interface timing (master mode) . . . . . . . . . . . . . . . . . . . . . 213 table 9-10 motorola bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 9-11 motorola bus interface timing (master mode) . . . . . . . . . . . . . . . . . . 218 table 9-12 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 9-13 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 9-14 transmit synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 9-15 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 9-16 receive synchronization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 peb 20256 e pef 20256 e data sheet 18 04.2001 table 9-17 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 9-18 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 peb 20256 e pef 20256 e data sheet 19 04.2001 peb 20256 e pef 20256 e munich256 overview data sheet 20 04.2001 1 munich256 overview the munich256 is a highly integrated protocol controller that implements hdlc, ppp and transparent (tma) protocol processing for 256 channels. an on-chip data management unit is optimized to transfer data packets via a pci interface by minimizing the bus load. the serial interface of the device can be configured in a 16-port mode and additionally in a 28-port mode. the 16-port mode provides a clock pin, a data pin and a frame synchronization pin for each port and direction. the 28-port mode provides a clock pin and a data pin per port and direction. in this mode frame boundaries are indicated by clock gaps. table 1-1 below shows the pin configuration and the supported frame structures in the 16-port mode and the 28-port mode. table 1-1 interface configuration port mode 16-port mode 28-port mode supported interfaces 1.544 mbit/s channelized x x 2.048 mbit/s channelized x x 4.096 mbit/s channelized x 8.192 mbit/s channelized x unchannelized x x supported pins receive data x x receive clock x x receive synchronization pulse x transmit clock x x transmit data x x transmit synchronization pulse x frame indication gapped clock x synchronization pulse x peb 20256 e pef 20256 e munich256 overview data sheet 21 04.2001 1.1 general features ? configurable port interface which operates in 16-port mode or 28-port mode. ? in 16-port mode protocol processing on up to 16 t1, e1, channelized 4 mbit/s, channelized 8 mbit/s or unchannelized links for frame relay, router or dslam applications with a maximum aggregate data rate of up to 90 mbit/s per direction at 66 mhz pci frequency ? in 28-port mode protocol processing on up to 28 t1, e1 or unchannelized links. t1, e1 frame boundaries are indicated by clock gaps ? support of 256 bidirectional channels, which can be assigned arbitrarily to a maximum of 16 links, for hdlc, ppp or transparent mode (tma) processing ? concatenation of any, not necessarily consecutive, time slots to logical channels on each physical link. supports ds0, fractional t1/e1 or t1/e1 channels ? additional support of unchannelized modes, with data rates of up to 45 mbit/s on port zero and 8.192 mbit/s on all other ports ? provides 32kb data buffer in transmit direction and 12kb data buffer in receive direction ? independently selectable pay load loops for each port ? provides a test function which allows to switch one out of 16 (28) ports to a test port ? system interface is a pci 32 bit, 66 mhz rev. 2.1 compliant bus interface, which supports configuration of subsystem id / subsystem vendor id via a serial eeprom interface ? integrates a local microprocessor master and slave interface (demultiplexed 16 bit address and data bus in intel mode or motorola mode) which allows access to the local bus via the pci bus or which can communicate with a pci host processor through an on-chip mailbox ? jtag boundary scan according to ieee1149.1 (5 pins) ? 0.25 m, 2.5v core technology ? i/os are 3.3v tolerant and have 3.3v driving capability ? package p-bga 388 (35mm x 35mm, pitch 1.27mm) ? full scan path and bist of on-chip rams for production test ? performance: 90 mbit/s data throughput per direction at 66 mhz ? estimated power consumption: 3w at 66 mhz ? also available as device with extended temperature range -40..+85 c peb 20256 e pef 20256 e munich256 overview data sheet 22 04.2001 1.2 logic symbol ? figure 1-1 munich256 16-port mode logic symbol munich256 peb 20256 e pef 20256 e spclk spload spo spi spcs v ss v dd25 v dd3 trst tms tdo tdi tck scan spi tm pci jtag rclk[15:0] rd[15:0] rsp[15:0] td[15:0] tclk[15:0] tsp[15:0] serial interface lmode la(12:0) ld(15:0) lhold/lbr lhlda/lbg lbgack lclk lcs0 lcs1 lbhe/lsize0 lint lrdy/ldtack lrd/lds lwr/lrdwr local bus lcs2 trsp ttd ttclk ttsp test and reference signals trd trclk tclk0 ad[31:0] c/be[3:0] par frame irdy trdy stop idsel perr serr req gnt clk rst inta devsel peb 20256 e pef 20256 e munich256 overview data sheet 23 04.2001 ? figure 1-2 munich256 28-port mode logic symbol 1.3 general system integration munich256 the munich256 provides the hdlc/ppp or transparent (tma) protocol handling for channelized or unchannelized applications with up to 16 links. protocol data is transferred to the packet ram via the pci bus and handled (e.g. for layer3 protocol handling) by a central cpu. an integrated mailbox allows to exchange information between a local cpu and the line card processor. munich256 peb 20256 e pef 20256 e ad[31:0] c/be[3:0] par frame irdy trdy stop idsel perr serr req gnt clk rst inta spclk spload spo spi spcs v ss v dd25 v dd3 trst tms tdo tdi tck scan spi tm pci jtag rclk[27:0] rd[27:0] td[27:0] tclk[27:0] serial interface lmode la(12:0) ld(15:0) lhold/lbr lhlda/lbg lbgack lclk lcs0 lcs1 lbhe/lsize0 lint lrdy/ldtack lrd/lds lwr/lrdwr local bus lcs2 ttd trd ttclk trclk tclk0 test and reference signals devsel peb 20256 e pef 20256 e munich256 overview data sheet 24 04.2001 ? figure 1-3 system integration of the munich256 transceiver, framer local cpu pci bus m256 bridge pci packet ram linecard processor peb 20256 e pef 20256 e pin description data sheet 25 04.2001 2 pin description 2.1 pin diagram 16-port mode munich256 (top view) figure 2-1 munich256 pin configuration 16-port mode vdd3 td(11) td(15) rclk (4) rd(4) td(12) rd(5) rd(6) rd(7) vdd3 rd(8) rd(9) rclk (7) rclk (8) rclk (9) vss td(6) td(5) td(4) td(3) rd(10) rclk (10) rd(11) rd(12) rclk (13) rclk (12) rd(13) td(2) td(0) td(1) tclko / trclk tclk (0) tdo nc12 tck trst nc14 nc15 nc13 nc11 res5 nc4 tsp(6) trsp rsp (7) ttsp res6 res3 nc26 nc27 nc25 nc30 lrd/ lds ld(4) ld(3) nc22 ld(1) ld(2) vss ld(0) vdd3 tms td(7) rclk (11) td(8) scan nc9 tdi nc10 rclk (5) nc8 td(10) td(9) td(13) tclk (4) td(14) trd tclk (1) tclk (6) ttclk vdd3 tclk (10) tclk (5) res9 rsp (10) rsp (9) tsp(0) tsp(1) tsp(5) rsp (3) rsp (6) rsp (2) tsp(4) tsp(7) rsp (5) rsp (4) res4 nc6 nc5 nc2 nc3 nc0 tclk (3) rd(14) rclk (15) rd(15) res21 rclk (14) ttd rd(0) rsp (0) res20 rclk (0) tsp(3) rsp (1) nc7 res7 tsp (8) rsp (8) res8 rsp (11) tclk (2) tsp (10) tsp(9) res11 la(3) la(8) ad(1) rst spo la(6) lbhe/ lsize0 inta ad(2) ad(4) la(12) la(7) la(11) ad(12) ad(14) ad(15) ad(13) ld(12) ld(9) ld(6) la(1) ld(10) ld(13) la(0) vdd3 ld(14) ld(15) la(4) nc29 c/ be(2) stop nc31 nc28 fram e vss vss vss vss vss vss vss vss vss vss ad(16) vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss nc1 vss vss vss vss vss vss vss vss vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 ad(22) c/ be(3) vdd3 vdd3 ad(31) vdd3 spclk vdd3 res14 vdd3 vdd3 rclk (6) vdd3 vdd3 vdd3 vdd3 vdd3 tsp(2) vdd3 vdd3 vdd3 vdd3 vdd3 tclk (13) rd(3) vdd3 tclk (14) lbgac k rd(2) rclk (1) lmod e lcs2 lwr/ lrd wr nc17 nc23 ld(5) nc16 nc18 nc20 rclk (2) rclk (3) lcs1 rd(1) lclk lhold /lbr lcs0 lhlda/ lbg lint lrdy rsp (12) res12 res10 tsp (11) tclk (8) tclk (7) tclk (15) tclk (12) tclk (9) tclk (11) ld(7) ld(2) la(5) la(10) la(9) ad(0) ad(3) ad(7) ad(5) ad(6) ad(27) ad(30) ad(26) req clk ad(29) gnt sploa d spi tsp (15) ad(20) ad(18) ad(21) ad(19) ad(23) vdd3 ad24 idsel ad(25) ad(28) ad(8) c/ be(0) ad(9) ad(10) ad(11) c/ be(1) par serr irdy ad(17) rsp (15) rsp (13) spcs tsp (13) tsp (14) res16 res13 rsp (14) tsp (12) res15 nc19 ld(8) ld(11) nc21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af perr trdy nc24 devse l peb 20256 e pef 20256 e pin description data sheet 26 04.2001 2.2 pin diagram 28-port mode munich256 (top view) figure 2-2 munich256 pin configuration 28-port mode vdd3 td(11) td(15) rclk (4) rd(4) td(12) rd(5) rd(6) rd(7) vdd3 rd(8) rd(9) rclk (7) rclk (8) rclk (9) vss td(6) td(5) td(4) td(3) rd(10) rclk (10) rd(11) rd(12) rclk (13) rclk (12) rd(13) td(2) td(0) td(1) tclko / trclk tclk (0) tdo nc12 tck trst nc14 nc15 nc13 nc11 tclk ((16) nc4 rd(18) tclk ((12) rclk (19) tclk ((13) tclk ((17) tclk ((14) nc26 nc27 nc25 nc30 lrd/ lds ld(4) ld(3) nc22 ld(1) ld(2) vss ld(0) vdd3 tms td(7) rclk (11) td(8) scan nc9 tdi nc10 rclk (5) nc8 td(10) td(9) td(13) td(16) td(14) trd tclk (1) td(18) ttclk vdd3 td(22) td(17) tclk ((20) rclk (22) rclk (21) tclk (4) tclk ((6) rd(17) tclk ((11) rclk (18) tclk ((9) rd(16) rd(19) rclk (17) rclk (16) tclk ((15) nc6 nc5 nc2 nc3 nc0 tclk ((3) rd(14) rclk (15) rd(15) res21 rclk (14) ttd rd(0) tclk ((5) res20 rclk (0) tclk ((10) tclk ((7) nc7 tclk ((18) rd(20) rclk (20) tclk ((19) rclk (23) tclk (2) rd(22) rd(21) tclk ((22) la(3) la(8) ad(1) rst spo la(6) lbhe/ lsize0 inta ad(2) ad(4) la(12) la(7) la(11) ad(12) ad(14) ad(15) ad(13) ld(12) ld(9) ld(6) la(1) ld(10) ld(13) la(0) vdd3 ld(14) ld(15) la(4) nc29 c/ be(2) stop nc31 nc28 fram e vss vss vss vss vss vss vss vss vss vss ad(16) vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss nc1 vss vss vss vss vss vss vss vss vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd25 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 vdd3 ad(22) c/ be(3) vdd3 vdd3 ad(31) vdd3 spclk vdd3 tclk ((25) vdd3 vdd3 rclk (6) vdd3 vdd3 vdd3 vdd3 vdd3 tclk ((8) vdd3 vdd3 vdd3 vdd3 vdd3 td(25) rd(3) vdd3 td(26) lbgac k rd(2) rclk (1) lmod e lcs2 lwr/ lrd wr nc17 nc23 ld(5) nc16 nc18 nc20 rclk (2) rclk (3) lcs1 rd(1) lclk lhold /lbr lcs0 lhlda/ lbg lint lrdy rclk (24) tclk ((23) tclk ((21) rd(23) td(20) td(19) td(27) td(24) td(21) td(23) ld(7) ld(2) la(5) la(10) la(9) ad(0) ad(3) ad(7) ad(5) ad(6) ad(27) ad(30) ad(26) req clk ad(29) gnt sploa d spi rd(27) ad(20) ad(18) ad(21) ad(19) ad(23) vdd3 ad24 idsel ad(25) ad(28) ad(8) c/ be(0) ad(9) ad(10) ad(11) c/ be(1) par serr irdy ad(17) rclk (27) rclk (25) spcs rd(25) rd(26) tclk ((27) tclk ((24) rclk (26) rd(24) tclk ((26) nc19 ld(8) ld(11) nc21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af perr trdy nc24 devse l peb 20256 e pef 20256 e pin description data sheet 27 04.2001 2.3 pin definition and functions signal type definitions: the following signal type definitions are partly taken from the pci specification rev. 2. 1: i input is a standard input- only signal. o totem pole output is a standard active driver. t/s, i/o tri-state or i/o is a bidirectional, tri-state input/output pin. s/t/s sustained tri-state is an active low tri-state signal owned and driven by one and only agent at a time. the agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. a new agent cannot start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it. a pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. o/d open drain allows multiple devices to share a line as a wire-or. a pull- up is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. signal name conventions: ncn no-connect pin n such pins are not bonded with the silicon. although any potential at these pins will not impact the device it is recommended to leave them unconnected. no-connect pins might be used for additional functionality in later versions of the device. leaving them unconnected will guarantee hardware compatibility to later device versions. reserved reserved pins are for vendor specific use only and should be connected as recommended to guarantee normal operation. note: the signal type definition specifies the functional usage of a pin. this does not reflect necessarily the implementation of a pin, e.g. a pin defined of signal type ?input? may be implemented with a bidirectional pad. peb 20256 e pef 20256 e pin description data sheet 28 04.2001 2.4 pci bus interface ? pin no. symbol input (i) output (o) function t3, t4, u1, u3, v2, w1, w2, v4, aa2, w4, ac1, ab2, y3, y4, ad1, ac2, ac8, ae6, ad8, af6, ac9, ae8, af7, ad10, ac11, af8, af10, ad11, ac12, ae11, ad12, af11 ad(31:0) t/s address/data bus a bus transaction consists of an address phase followed by one or more data phases. when the munich256 i s the bus master, ad(31:0) are outputs in the address phase of a transaction. during the data phases, ad(31:0) remain outputs for write transactions, and become inputs for read transactions. when the munich256 i s bus slave, ad(31:0) are inputs in the address phase of a transaction. during the data phases, ad(31:0) remain inputs for write transactions, and become outputs for read transactions. ad(31:0) are tri-state when the munich256 i s not involved in the current transaction. ad(31:0) are updated and sampled on the rising edge of clk. peb 20256 e pef 20256 e pin description data sheet 29 04.2001 v3, aa4, ad7, ae9 c/ be (3:0) t/s command/byte enable during the address phase of a transaction, c/ be (3:0) define the bus command. during the data phase, c/ be (3:0) are used as byte enable lines. the byte enable lines are valid for the entire data phase and determine which byte lanes carry meaningful data. c/ be (0) applies to byte 0 (lsb) and c/ be (3) applies to byte 3 (msb). when the munich256 i s bus master, c/ be (3:0) are outputs. when the munich256 i s bus slave, c/ be (3:0) are inputs. c/ be (3:0) are tri-stated when the munich256 i s not involved in the current transaction. c/ be (3:0) are updated and sampled on the rising edge of clk. af4 par t/s parity par is even parity across ad(31:0) and c/ be (3:0). par is stable and valid one clock after the address phase. par has the same timing as ad(31:0) but delayed by one clock. when the munich256 i s master, par is output during address phase and write data phases and input during read data phase. when the munich256 i s slave, par is output during read data phase and input during write data phase. par is tri-stated when the munich256 i s not involved in the current transaction. parity errors detected by the device a re indicated on perr output. par is updated and sampled on the rising edge of clk. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 30 04.2001 ab3 frame s/t/s frame frame indicates the beginning and end of an access. frame is asserted to indicate a bus transaction is beginning. while frame is asserted, data transfers continue. when frame is deasserted, the transaction is in the final phase. when the munich256 i s bus master, frame is an output. when the munich256 i s bus slave, frame is an input. frame is tri-stated when the munich256 i s not involved in the current transaction. frame is updated and sampled on the rising edge of clk. ac6 irdy s/t/s initiator ready irdy indicates the bus master?s ability to complete the current data phase of the transaction. it is used in conjunction with trdy . a data phase is completed on any clock where both irdy and trdy are sampled asserted. during a write, irdy indicates that valid data is present on ad(31:0). during a read, it indicates the master is prepared to accept data. wait cycles are inserted until both irdy and trdy are asserted together. when the munich256 i s bus master, irdy is an output. when the munich256 i s bus slave, irdy is an input. irdy is tri- stated, when the munich256 i s not involved in the current transaction. irdy is updated and sampled on the rising edge of clk. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 31 04.2001 ad5 trdy s/t/s target ready trdy indicates a slave?s ability to complete the current data phase of the transaction. during a read, trdy indicates that valid data is present on ad(31:0). during a write, it indicates the target is prepared to accept data. when the munich256 i s master, trdy is an input. when the munich256 i s slave, trdy is an output. trdy is tri- stated, when the munich256 i s not involved in the current transaction. trdy is updated and sampled on the rising edge of clk. af3 stop s/t/s stop stop is used by a slave to request the current master to stop the current bus transaction. when the munich256 i s bus master, stop is an input. when the munich256 i s bus slave, stop is an output. stop is tri-stated, when the munich256 i s not involved in the current transaction. stop is updated and sampled on the rising edge of clk. aa1 idsel i initialization device select when the munich256 i s slave in a transaction, where idsel is active in the address phase and c/ be (3:0) indicates an configuration read or write, the munich256 a ssumes a read or write to a configuration register. in response, the munich256 a sserts devsel during the subsequent clk cycle. idsel is sampled on the rising edge of clk. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 32 04.2001 ae4 devsel s/t/s device select when activated by a slave, it indicates to the current bus master that the slave has decoded its address as the target of the current transaction. if no bus slave activates devsel within six bus clk cycles, the master should abort the transaction. when the munich256 i s bus master, devsel is input. if devsel is not activated within six clock cycles after an address is output on ad(31:0), the munich256 aborts the transaction. when the munich256 is bus slave, devsel is output. devsel is tri-stated, when the munich256 is not involved in the current transaction. ac7 perr s/t/s parity error when activated, indicates a parity error over the ad(31:0) and c/ be (3:0) signals (compared to the par input). it has a delay of two clk cycles with respect to ad and c/ be (3:0) (i.e., it is valid for the cycle immediately following the corresponding par cycle). perr is asserted relative to the rising edge of clk. ae5 serr o/d system error the munich256 asserts this signal to indicate an address parity error and report a fatal system error. serr is an open drain output activated on the rising edge of clk. t2 req t/s request used by the munich256 to request control of the pci bus. it is tri-state during reset. req is activated on the rising edge of clk. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 33 04.2001 t1 gnt i grant this signal is asserted by the arbiter to grant control of the pci to the munich256 in response to a bus request via req . after gnt is asserted, the munich256 will begin a bus transaction only after the current bus master has deasserted the frame signal. gnt is sampled on the rising edge of clk. r4 clk i clock provides timing for all pci transactions. most pci signals are sampled or output relative to the rising edge of clk. the pci clock is used as internal system clock. the maximum clk frequency is 66 mhz. r3 rst i reset an active rst signal brings all pci registers, sequencers and signals into a consistent state. all pci output signals are driven to high impedance. ac13 inta o/d interrupt request when an interrupt status is active and unmasked, the munich256 activates this open-drain output. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 34 04.2001 2.5 spi interface ? pin no. symbol input (i) output (o) function p2 spi i spi serial input spi is a data input pin, where data coming from an external eeprom is shifted in. spi is sampled on the rising edge of spclk. a pull-up resistor is recommended if the spi interface is not used. p1 spo o spi serial output spo is a push/pull serial data output pin. opcodes, byte addresses and data is updated on the falling edge of spclk. it is tri-state during reset. n4 spclk o spi clock signal spclk controls the serial bus timing of the spi bus. spclk is derived from the pci bus clock with a frequency of 1/78 of the pci bus clock. it is tri-state during reset. n3 spcs o spi chip select spcs is used to select an external eeprom. it is tri-state during reset. p4 spload i enable spi load functionality connecting spload to v dd3 enables the spi bus after reset. in this case parts of the pci configuration space can be configured via an external eeprom. peb 20256 e pef 20256 e pin description data sheet 35 04.2001 2.6 local microprocessor interface ? pin no. symbol input (i) output (o) function w24 lmode i local bus mode by connecting this pin to either v ss or v dd3 the bus interface can be adapted to either intel or motorola environment. lmode = v ss selects intel bus mode. lmode = v dd3 selects motorola bus mode. y24 lclk o local clock reference output clock derived from the pci clock. ae13, af13, af14, ae14, af16, ac14, ad15, ae16, af17, ac15, ad16, af19, ae18 la(12:0) i/o address bus these input address lines select one of the internal registers for read or write access. note: only la(7:0) are evaluated during read/write accesses to the munich256. in local bus master mode the address lines are output. if local bus master functionality is disabled these pins are input only. ac16, ad17, af20, ae19, af21, ac18, ad19, ae21, ad20, ac19, af23, ae24, af25, ae26, ad25, ab23 ld(15:0) i/o data bus bidirectional tri-state data lines. y23 lcs0 i chip select this active low signal selects the munich256 as bus slave for read/write operations. peb 20256 e pef 20256 e pin description data sheet 36 04.2001 ac24 lrd or lds i/o i/o read (intel bus mode) this active low signal selects a read transaction. data strobe (motorola bus mode) this active low signal indicates that valid data has to be placed on the data bus (read cycle) or that valid data has been placed on the data bus (write cycle). ab24 lwr or lrd wr i/o i/o write enable (intel bus mode) this active low signal selects a write cycle. read write signal (motorola bus mode) this input signal distinguishes write from read operations. aa23 lrdy or dtack i/o i/o ready (intel bus mode) this signal indicates that the current bus cycle is complete. the munich256 asserts lrdy during a read cycle if valid output data has been placed on the data bus. in write direction lrdy will be asserted when input data has been latched. in local bus master mode munich256 evaluates lrdy to finish a transaction. data transfer acknowledge (motorola bus mode) this active low input indicates that a data transfer may be performed. during a read cycle data becomes valid at the falling edge of dtack . the data is latched internally and the bus cycle is terminated. during a write cycle the falling edge of dtack marks the latching of data and the bus cycle is terminated. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 37 04.2001 ac26 lint i/od interrupt request this line indicates general interrupt requests of the mailbox. the interrupt sources can be masked via registers. in local bus master mode the munich256 can monitor external interrupts indicated via lint . ac25, w23 lcs2 , lcs1 o chip select 2, 1 these signals select external peripherals when munich256 is the local bus master. as long as the local bus master functionality is disabled these outputs are set to tri-state. ad13 lbhe or lsize0 o o byte high enable (intel bus mode) in local bus master mode this signal indicates a data transfer on the upper byte of the data bus ld(15:8). this signal has no function in slave mode. when local bus master functionality is disabled this output is tri-state. byte access (motorola bus mode) in local bus master mode this signal indicates byte transfers. this signal has no function when the munich256 is local bus slave. when local bus master functionality is disabled this output is tri-state. aa25 lhold or lbr o o bus request (intel bus mode) this pin indicates a requests to become local bus master. when local bus master functionality is disabled this output is tri-state. bus request (motorola bus mode) lbr indicates a request to become local bus master. when local bus master functionality is disabled this output is set to tri-state. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 38 04.2001 ? ab25 lhlda or lbg i i hold (intel bus mode) lhlda indicates that the external processor has released control of the local bus. bus grant (motorola bus mode) lbg indicates that the munich256 may access the local bus. v23 lbgack o bus grant acknowledge (motorola bus mode) lbgack is driven low when the munich256 has become bus master. when local bus master functionality is disabled this output is tri-state. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 39 04.2001 2.7 serial interface 16-port mode ? pin no. symbol input (i) output (o) function m24 trd o test receive data in serial test mode the incoming data stream of one selected port is directly feeded to this output. when test breakout functionality is disabled this output is tri-state. c15 tclko or trclk o o transmit clock out this signal provides a clock reference for transmit data of high speed port zero. test receive clock in serial test mode the receive clock of one selected port is directly feeded to this output. b5 trsp o test receive synchronization pulse in serial test mode the receive synchronization of one selected port is directly feeded to this output. when test breakout functionality is disabled this output is tri-state. n26 ttclk o test transmit clock in serial test mode the clock provided via ttclk replaces the transmit clock output of the selected transmit line. when test breakout functionality is disabled this output is tri-state. c12 ttd i test transmit data in serial test mode the data stream provided via ttd replaces the transmit data stream of the selected transmit line. c5 ttsp o test transmit synchronization pulse in serial test mode the transmit synchronization pulse of one selected port is directly feeded to this output. when test breakout functionality is disabled this output is tri-state. peb 20256 e pef 20256 e pin description data sheet 40 04.2001 r23, v25, u26, r24, t25, p24, t26, p25, p26, n25, n23, l26, b14, c14, d14, a16 tclk(15:0) i transmit clock this signal provides the data clock for td. t1/ds1 24-channel 1.544 mhz cept 32-channel 2.048 mhz 64-channel 4.096 mhz 128-channel 8.192 mhz unchannelized: up to 45 mhz on port zero or 8.192 mhz on every other port. k26, m23, l25, h26, l23, d20, b22, a23, c20, d19, b21, c19, a21, c16, b16, d15 td(15:0) o transmit data serial data sent by this output port is push-pull for active bits in the pcm frame and tri-state for inactive bits. transmit data can be updated on the rising or falling edge of the transmit clock. n1, m3, l2, l3, f1, f2, e2, f4, b6, d7, a7, c8, a8, c9, c10, d11 tsp(15:0) i transmit synchronization pulse this signal provides the reference for the transmit frame synchronization. a low to high transition marks the frame boundary in a pcm frame (for details refer to chapter5.4.1 ). the transmit synchro- nization pulse is sampled on the rising or falling edge of the transmit clock. a13, d13, d16, a19, b18, b19, c26, g23, g24, h24, f26, k24, t24, t23, w25, c11 rclk(15:0) i receive clock this signal provides the data clock for rd. t1/ds1 24-channel 1.544 mhz cept 32-channel 2.048 mhz 64-channel 4.096 mhz 128-channel 8.192 mhz unchannelized: up to 45 mhz on port zero or 8.192 mhz on every other port. b13, a14, a17, c17, a20, d18, e25, d26, f25, j23, h25, j25, u24, w26, aa26, b11 rd(15:0) i receive data serial data is received at this pcm input port. receive data can be sampled on the rising or falling edge of the receive clock. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 41 04.2001 2.8 serial interface 28-port mode ? n2, m4, l1, l4, h4, g3, g4, d1, d6, a6, c7, d8, b8, d9, b9, a10 rsp(15:0) i receive synchronization pulse this signal provides the reference for the receive pcm frame synchronization. a low to high transition marks the frame boundary in a pcm frame (for details refer to chapter5.4.1 ). the receive synchronization pulse can be sampled on the rising or falling edge of the receive clock. d5, a4, b4, c4, e3, d2, h3, h2, j4, h1, j2, k4, k3, k1, d12, a11 res3..16 res20..21 reserved pins 3..16, 20..21 these pins are reserved in 16-pin mode. a pull-up resistor to v dd3 is recommended. pin no. symbol input (i) output (o) function c15 tclko or trclk o o transmit clock out this signal provides a clock reference for transmit data of high speed port zero. test receive clock in serial test mode the receive clock of one selected port is directly feeded to this output. m24 trd o test receive data in serial test mode the incoming data stream of one selected port is directly feeded to this output. n26 ttclk o test transmit clock in serial test mode the incoming receive clock of one selected port is directly feeded to this output. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 42 04.2001 c12 ttd i test transmit data in serial test mode the data stream provided via ttd replaces the transmit data stream of the selected transmit line. k1, k3, k4, j2, h1, j4, h2, h3, d2, e3, c4, b4, a4, d5, c5, b5, b8, a8, d9, c9, b9, c10, a10, d11, b14, c14, d14, a16 tclk(27:0) i transmit clock this signal provides the data clock for td. in framed modes (t1/e1) a clock gap indicates the frame boundary. t1/ds1 24-channel 1.544 mhz cept 32-channel 2.048 mhz unchannelized: up to 45 mhz on port zero or up to 8.192 mhz on every other port. r23, v25, u26, r24, t25, p24, t26, p25, p26, n25, n23, l26, k26, m23, l25, h26, l23, d20, b22, a23, c20, d19, b21, c19, a21, c16, b16, d15 td(27:0) o transmit data serial data sent by this output port is push-pull for active bits in the pcm frame and tri-state for inactive bits. output is tri- state until port is enabled for transmission. transmit data is updated on the rising or falling edge of the selected transmit clock. n2, m4, l1, l4, h4, g3, g4, d1, d6, a6, c7, d8, a13, d13, d16, a19, b18, b19, c26, g23, g24, h24, f26, k24, t24, t23, w25, c11 rclk(27:0) i receive clock this signal provides the data clock for rd. in framed modes (t1/e1) a clock gap indicates the frame boundary. t1/ds1 24-channel 1.544 mhz cept 32-channel 2.048 mhz unchannelized: up to 45 mhz on port zero or 8.192 mhz on every other port. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 43 04.2001 2.9 test interface ? n1, m3, l2, l3, f1, f2, e2, f4, b6, d7, a7, c8, b13, a14, a17, c17, a20, d18, e25, d26, f25, j23, h25, j25, u24, w26, aa26, b11 rd(27:0) i receive data serial data is received at this pcm input port. receive data can be sampled on the rising or falling edge of the receive clock. d12, a11 res20..21 reserved pins 20, 21 these pins are reserved in 28-port mode. a pull-up resistor to v dd3 is recommended. pin no. symbol input (i) output (o) function c25 tck i jtag test clock this pin is connected with an internal pull- up resistor. f23 tms i jtag test mode select this pin is connected with an internal pull- up resistor. a24 tdi i jtag test data input this pin is connected with an internal pull- up resistor. d24 tdo o jtag test data output pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 44 04.2001 2.10 power supply and no-connect pins ? b26 trst i jtag test reset this pin is connected with an internal pull- down r esistor. e24 scan i full scan path test when connected to v dd3 the munich256 works in a vendor specific test mode. it is recommended to connect this pin to v ss . pin no. symbol input (i) output (o) function af1, ae7, af9, ae12, ae15, af18, ae20, af26, ad3, ad24, ad26, y2, y25, v1, v26, r2, t12, t11, r12, r11, t14, t13, r14, r13, t16, t15, r16, r15, r25, p12, p11, n12, n11, p14, p13, n14, n13, p16, p15, n16, n15, m2, m12, m11, l12, l11, m14, m13, l14, l13, m16, m15, l16, l15, m25, j1, j26, g2, g25, c3, c24, d25, a1, b7, a9, b12, b15, a18, b20, a26 v ss i ground 0v all pins must have the same level. ae2, af5, ae10, af12, af15, ae17, af22, ae25, ab1, ab26, y1, y26, u2, u25, r1, r26, m1, m26, k2, k25, g1, g26, e1, e26, b2, a5, b10, a12, a15, b17, a22, b25 v dd25 i supply voltage 2.5v 0.25v all pins must have the same level. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e pin description data sheet 45 04.2001 ac4, ad6, ad9, ac10, ad14, ad18, ac17, ad21, ac23, aa3, aa24, w3, u4, v24, u23, p3, p23, n24, l24, j3, k23, j24, h23, f3, f24, d4, c6, d10, c13, d17, c18, c21, d23 v dd3 i supply voltage 3.3v 0.3v all pins must have the same level. e4, c1, b1, c2, a3, a2, b3, d3, b23, d21, c22, a25, e23, b24, c23, d22, ac22, ad23, ad22, ac21, ae22, ac20, af24, ae23, af2, ae3, ac5, ad4, ae1, ad2, ab4, ac3 nc0..31 no-connect pins 0..31 it is recommended not to connect these pins. pin no. symbol input (i) output (o) function peb 20256 e pef 20256 e general overview data sheet 46 04.2001 3 general overview 3.1 functional overview munich256 the munich256 is a highly integrated wan protocol controller that performs hdlc, ppp and transparent (tma) protocol processing on 256 full duplex serial channels and a configurable port mode with 16 or 28 links. dependent on the port mode a link can be operated in t1/e1, in channelized 4.096 mhz/ 8.192 mhz mode (16-port mode only) or in unchannelized mode. the internal framing function is switched off in this mode. in 16-port mode the system interface consists of one receive clock input, one receive synchronization pulse input and one receive data input for each receive line. in transmit direction each link consists of one transmit clock input, one transmit synchronization input and one transmit data output. synchronization pulses are not supported in unchannelized mode. in 28-port mode the system interface consists of a receive clock input and a receive data input. in transmit direction a transmit clock input and a transmit data output is provided. frame boundaries are indicated by clock gaps. the device provides a maximum aggregate data rate of 90 mbit/s per direction, assuming a pci frequency of 66 mhz (45 mbit/s at 33 mhz). the following clock rates are supported where the sum of all clock rates does not exceed the above throughput limitation: in 16-port mode: ? t1 mode with 1.544 mhz on any port. ? e1 mode with 2.048 mhz on any port. ? channelized mode with 4.096 mhz on any port. ? channelized mode with 8.192 mhz on any port. ? unchannelized mode with up to 45 mhz on port zero. ? unchannelized mode with up to 8.192 mhz on all other ports. in 28-port mode: ? t1 mode (1.544 mhz) with gapped clock on any port. ? e1 mode (2.048 mhz) with gapped clock on any port. ? unchannelized mode with up to 45 mhz on port zero. ? unchannelized mode with up to 8.192 mhz on all other ports. a variety of loop modes is provided to support remote as well as inloop testing of the device. two bus interfaces, a pci rev. 2.1 compliant bus interface and a 16 bit intel/motorola style bus interface, connect the device to system environment. device configuration and peb 20256 e pef 20256 e general overview data sheet 47 04.2001 channel operation is provided through the pci bus interface. the local bus interface provides access to the internal mailbox. the munich256 supports pci pnp capability by loading the subsystem id and the subsystem vendor id via a spi interface into the pci configuration space. 3.2 block diagram ? figure 3-1 munich256 block diagram 3.3 internal interface the device consists of several macro functions as shown in figure 3-1 . the internal modules are connected by busses/signals according to infineons on-chip bus. the main busses are: ? the initiator bus, on which the dma requests of the data management units and the interrupt controller are arbitrated and funneled into the pci interface. ? the configuration busses, which serve as the standard programming interface to access the chip internal registers and functions either via pci bus or via the local bus interface. port interface interrupt fifo mailbox/ bridge protocol handler internal buffer data management unit pci interface local bus interface master/slave interrupt controller serial line interface pci local up interface initiator bus spi tm 0 1 15 (27) jtag interface jtag loop buffer configuration bus i configuration bus ii interrupt bus i interrupt bus ii spi tm interface timeslot handler testport peb 20256 e pef 20256 e general overview data sheet 48 04.2001 ? the interrupt busses, which collect all interrupt information and forward them to the corresponding interrupt handler. the chip?s core functions are all operated with the pci clock. transfers between clocking regions (serial clocks and system clock) are implemented only in the serial interface. 3.4 block description the following section gives a brief overview to the function of each block. for a detailed description of each function refer to ? functional description ? on page51 . serial port interface the serial port interface consists of the subfunctions receive and transmit. this block provides the function of serial/parallel and parallel/serial conversion for up to 16 (or 28 when configured for 28 port mode) incoming and outgoing serial data streams. serial data is then transferred between the internal clocking system, which is derived from the pci clock, and the various line clocks. this provides a unique clocking scheme on the internal interfaces. the aggregate bandwidth of all enabled ports can be up to 90 mbit/ s in each direction with a pci clock frequency of 66mhz. t ime slot assigner the time slot assigner exchanges data with the serial interface on a 8 bit parallel bus, thus funneling all data of up to 28 interfaces. the time slot assigner provides freely programmable mapping of any time slot or any combination of time slots to 256 logical channels. a programmable mask can be provided to allow subchanneling of the available time slots which allows channel data rates starting at 8kbit/s. at the protocol machine interface the time slot assigner and the protocol machine exchanges channel oriented data (8 bit) together with the time slots masks. protocol handler two protocol machines, one for receive direction and one for transmit direction, provide protocol handling for up to 256 logical channels and a maximum serial aggregate data rate of up to 90 mbit/s per direction. the protocol machines implement four modes, which can be programmed independently for each logical channel: hdlc, bit-synchronous ppp, octet-synchronous ppp and transparent mode a, including frame synchronous tma. internal buffer the internal buffers provides channelwise buffering of raw (unformatted/deformatted) data for 256 logical channels. channel specific thresholds can be programmed peb 20256 e pef 20256 e general overview data sheet 49 04.2001 independently in transmit and receive direction. in order to avoid transmit underrun conditions each transmit channel has two control parameters for smoothing the filling/ emptying process (transmit forward threshold, transmit refill threshold). in receive direction each channel has a receive burst threshold. to avoid unnecessary waste of bus bandwidth, e.g. in case of transmission errors, the receive buffer provides the capability to discard frames which are smaller than a programmable threshold. data management units the data management units provide direct data transfer between the system memory and the internal buffers. each channel has an associated linked list of descriptors, which is located in system memory and handled by the data management units. this linked list is the interface between the system processor and the munich256 for exchange of data packets. the descriptors and the data packets can be stored arbitrarily in 32 bit address space of system memory, thus allowing full scatter/gather assembly of packets. in order to optimize pci bus utilization, each descriptor is read in one burst and h el d on-chip afterwards. interrupt controller two interrupt controller s manage internal interrupts. interrupts from the mailbox are passed in the form of interrupt vectors to an internal interrupt fifo which can be read from the local bus. all system, port and channel related interrupt information is p assed to the main interrupt controller which is connected to the pci system. a programmable dma with nine channels stores these interrupts in the form of interrupt vectors in different interrupt queues in system memory. pci interface the pci interface unit combines all dma requests from the internal data management unit and the interrupt controller and translates them into pci rev. 2.1 compliant bus accesses. the pci interface optionally includes the function of loading the subsystem vendor id and the subsystem id from an external spi compliant eeprom. mailbox, internal bridge and global registers the mailbox is used to exchange data between the pci attached microprocessor and the local bus microprocessor and provides a doorbell function between the two interfaces. controlled by an arbiter an internal bridge connects the configuration bus i and the configuration bus ii. it is not possible to access the configuration bus i and therefore the ?hdlc? registers or the pci bridge from the local bus. peb 20256 e pef 20256 e general overview data sheet 50 04.2001 local bus interface the local bus interface provides access between t he local microprocessor and the on- chip configuration bus ii , in order to access the mailbox. the local bus interface provides a switchable intel-style or motorola-style processor interface. jtag boundary scan logic according to ieee 1149.1. peb 20256 e pef 20256 e functional description data sheet 51 04.2001 4 functional description 4.1 port handler the port handler is the interface between the serial ports and the chip internal protocol functions. it converts incoming serial data into parallel data for further internal processing and in the outgoing direction it converts parallel data into a serial bit stream. 4.1.1 selectable port configuration the serial interface of the device can be configured in a 16-port mode and additionally in a 28-port mode. the 16-port mode provides a clock pin, a data pin and a frame synchronization pin for each port and direction. the 28-port mode provides a clock pin and a data pin per port and direction. in this mode frame boundaries are indicated by clock gaps. table 4-1 and figure 4-1 respectively show the pin configuration and the supported frame structures in the 16-port mode and the 28-port mode. table 4-1 interface configuration port mode 16-port mode 28-port mode supported interfaces 1.544 mbit/s channelized x x 2.048 mbit/s channelized x x 4.096 mbit/s channelized x 8.192 mbit/s channelized x unchannelized x x supported pins receive data x x receive clock x x receive synchronization pulse x transmit clock x x transmit data x x transmit synchronization pulse x frame indication peb 20256 e pef 20256 e functional description data sheet 52 04.2001 ? figure 4-1 port configuration 4.1.2 external timing mode each transmit port is clocked using the external timing reference tclk(x). since all ports have their individual transmit clock each port can be operated independent of each other. gapped clock x synchronization pulse x tclk td rclk rd tsp rsp port clocking domain internal clocking domain clock synchronization tclk td rclk rd transmit path receive path port clocking domain internal clocking domain clock synchronization transmit path receive path a) interface configuration in 16-port mode b) interface configuration in 28-port mode peb 20256 e pef 20256 e functional description data sheet 53 04.2001 the same functionality as given for the transmit direction applies in receive direction. 4.1.3 local port loop a local port loop can be closed in the port interface. it mirrors the outgoing bit stream of one port to the receive part of the same port. this allows to prepare data in system memory, which is processed by the munich256 in transmit direction, mirrored to the receiver and stored in system memory again. in order to ensure that the local port loop works even without an incoming receive clock, the receiver of the selected port is operated with the transmit clock. when closing the local port loop, the corresponding transmit clock tclk(x) and transmit frame synchronization pulse tsp(x) are used to operate the transmitter and the receiver. receive data rd(x), the receive clock rclk(x) and the receive synchronization pulse rsp(x) are ignored in that case. ? figure 4-2 local port loop receive port timeslot assigner timeslot assigner transmit port protocol machine protocol machine tclk(x) td(x) rd(x) rclk(x) rsp(x) tsp(x) to pci from pci peb 20256 e pef 20256 e functional description data sheet 54 04.2001 4.1.4 remote payload loop the munich256 supports a remote payload loop for each of the 16 (28) lines), where the incoming serial data stream of a selected port is mirrored to the outgoing serial data stream of the same port. the f-bit (t1 mode) is not looped. in receive direction the payload is stored in an internal loop buffer and in transmit direction this payload data is taken from the loop buffer and inserted in the outgoing bit stream. this internal loop buffer compensates for receive clock and transmit clock jitter. nevertheless, the average clock rate of the receive port and the transmit port must be the same. after first activation the payload of one frame is written to the loop fifo. then the time slot assigner starts reading data bytes out of the loop buffer and inserts them into the transmit data path. due to a receive/transmit clock jitter the read pointer may move towards the write pointer. in case the distance between write pointer and read pointer is equal plus/minus 1 byte a slip of the read pointer will occur. for ports configured in 8.192 mbit/s mode the receive clock and the transmit clock must be synchronous. ? figure 4-3 remote payload loop timeslot assigner timeslot assigner loop buffer protocol machine protocol machine to pci fro m pci + 1 in t1/e1 mode only. framer is disabled in unchannelized mode. rd(x) rclk(x) rsp(x) receive port tclk(x) td(x) tsp(x) transmit port peb 20256 e pef 20256 e functional description data sheet 55 04.2001 4.1.5 remote channel loopback a remote channel loop can be switched for one logical channel at a time. incoming serial data located in the receive payload of one port is mirrored to the corresponding transmit channel (same channel number). an internal jitter attenuator compensates jitter between receive clock and transmit clock. nevertheless, the average clock rate of the receive port and the transmit port must be the same. after first activation of the loop 32 receive bytes are written to the loop fifo. then the time slot assigner starts reading data bytes out of the loop buffer and inserts them into the transmit data path. hence, the initial distance between the fifo read pointer and the fifo write pointer is 32 bytes. due to a receive/ transmit clock jitter the read pointer may move towards the write pointer. in case the distance between write pointer and read pointer is equal plus/minus 1 byte a slip of the read pointer will occur. in channelized and unchannelized mode the transmit and receive masks of all time slots belonging to the looped channel must be the same. the aggregate bit rate of the transmit section and the aggregate bit rate of the receive section has to be identical. in receive direction incoming data of the selected channel is stored in the loop buffer. in transmit direction data is clocked out of the loop buffer and transmitted in the time slots of the selected channel. received data is processed normally. the remote channel loop can also be used to loop the complete payload except the ?f?- bit (t1). therefore one logical channel must be setup which includes all payload time slots. ? figure 4-4 remote channel loop tclk(x) td(x) rd(x) rclk(x) rsp(x) tsp(x) timeslot assigner timeslot assigner loop buffer protocol machine protocol machine to pci from pci + receive port transmit port peb 20256 e pef 20256 e functional description data sheet 56 04.2001 4.1.6 test breakout the test breakout function provides the capability to multiplex one of the incoming 16 (28) receive links to the outgoing test receive port, that is the incoming receive clock signal rclk(x) is mapped to the test receive clock output trclk, the receive synchronization pulse rsp(x) is mapped to trsp (16-port mode only) and the incoming receive data signal rd(x) is mapped to the test data output trd. in the opposite direction one of the 16 (28) transmit data output signals td(x) can be replaced with the test transmit data signal ttd. furthermore the corresponding transmit synchronization pulse input tsp(x) (16-port mode only) and the transmit clock input signal tclk(x) can be monitored on the test port outputs ttsp and ttclk. there is no processing function in the data path. each output signal is a buffered version of the corresponding input signal, e.g. output signal td(x) is a buffered version of the incoming signal ttd. ? figure 4-5 test breakout tclk(15) tsp(15) trclk trd ttclk ttd td(15) rclk(15) rsp(15) rd(15) tclk(0) tsp(0) td(0) rclk(0) rsp(0) rd(0) trsp ttsp to/from time slot assigner tclk(27) trclk trd ttclk ttd td(27) rclk(27) rd(27) tclk(0) td(0) rclk(0) rd(0) to/from time slot assigner a) test breakout in 16-port mode b) test breakout in 28-port mode peb 20256 e pef 20256 e functional description data sheet 57 04.2001 4.2 time slot handler 4.2.1 channelized modes the time slot handler assigns any combination of time slots of ports configured in t1 or e1 , 4.096 mhz or 8.192 mhz mode to logical channels. the assigned time slots are connected internally and the bit stream of one logical channel is mapped continuously over the selected time slots. since the receiver and the transmitter operate independently of each other, the assignment of time slots to logical channels can be done separately in receive and transmit direction. any time slot can be assigned to any channel and any sequence of time slots can be assigned to one channel. in normal operation each time slot consists of eight bits and all bits are used for data transmission. an available mask function provides the capability to mask selected bits, which in turn are disabled for data transmission. this provides the possibility to operate time slots with less than 64 kbit/s throughput. so, instead of mapping the bit stream of one logical channel over all bits of the assigned time slots, the bit stream is mapped continuously over all unmasked bits of the time slots belonging to that channel. masked bits are tri-stated in transmit direction. in receive direction masked data bits are discarded. figure4-6 shows a simple assignment process. in this case one port is configured in e1 mode and time slots two and three are assigned to logical channel 5. the bit mask of time slot two is set to fe h , which disables bit zero of that time slot, and the bit mask of the third time slot is set to fd h , which disables bit one. peb 20256 e pef 20256 e functional description data sheet 58 04.2001 ? figure 4-6 time slot assignment in channelized modes 4.2.2 unchannelized mode in unchannelized mode the complete incoming and outgoing serial bit stream belongs to one logical channel. although unchannelized mode does not have a time slot scheme, this mode is handled internally the same way as a port configured in t1 mode. therefore the time slot assignment must be done as in t1 mode, with exception that ?time slots? zero to 23 must be assigned to one channel and that no time slot may be set to inhibit. the function of bit masks, which is available in t1, e1, 4.096 mhz or 8.192 mhz mode, is not available in unchannelized mode. each bit of the time slots 0-23 must be enabled, setting the masks to ff h . furthermore unchannelized mode does not provide the function of synchronizing bits to an external frame synchronization pulse. 0 1 2 29 30 31 0 1 2 29 30 31 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 frame 1 frame 2 timeslot 2 timeslot 3 3 3 7 6 1 0 1 1 1 1 1 1 1 0 timeslot mask 0 1 1 1 1 1 1 1 timeslot mask time example configuration: port three in mode e1. timeslot 2 and 3 are assigned to channel 5. bit 0 of timeslot 2 and bit 1 of timeslot 3 are masked. programming sequence: 1 . por t mode configuration 3 h 0 31 pmiar pmr 8 h 2. timeslot assignment register data tsaia tsad tsaia tsad 1 1 1 0 1 1 1 1 5 h 1 1 1 1 0 1 1 1 5 h 3 h 2 h 3 h 3 h select port 3 e1 mode select port 3, timeslot 2 set channel 5, mask select port 3, timeslot 3 set channel 5, mask peb 20256 e pef 20256 e functional description data sheet 59 04.2001 4.3 data management unit each packet or part of a packet is referenced by a descriptor. the descriptors form a link list, thus connecting all packets together. packet data as well as descriptors are located in system memory. both the munich256 and the system cpu operate on these data structures. each logical channel has its dedicated linked list of descriptors, one for receive direction and one for transmit direction. this type of data structure allows channel specific memory organization which can be specified by the system processor. it provides an optimized way to transfer data packets between the system processor and the munich256. the munich256 has a flexible dma controller to transfer data either from the internal receive buffer to the shared memory (receive direction) or from the shared memory to the internal transmit buffer (transmit direction). each dma works on one linked list. each linked list located in system memory is associated with one of the 256 transmit channels or one of 256 receive channels. the address generator of the dma controller supports full link list handling. descriptors are stored independently from the data buffers, thus allowing full scatter/gather assembly and disassembly of data packets. 4.3.1 descriptor concept a descriptor is used to build a linked list, where each member of the linked list points to a data section. a descriptor consists of four dwords 1) . the first three dwords, containing link and packet information, are provided by the system cpu and the last dword contains status information, which is written when the munich256 has finished operation on a descriptor. the data section itself can be of any size up to the maximum size of 65535 bytes per descriptor and is defined in the first dword of a descriptor. each logical data packet can be split into one or multiple parts, where each part is referenced by one descriptor, and all parts are referenced by a linked list of descriptors. the descriptor containing the last part of a data packet is marked with a frame end bit. the descriptor following the marked descriptor therefore contains the beginning of the next data packet ( figure 4-7 ). the last descriptor in a linked list is marked with a hold indication. for ease of programming the transmit descriptor and the receive descriptor are structured the same way, thus allowing to link a receive descriptor directly into the linked list of the transmit queues with minimum descriptor processing. 1) peb 20256 e pef 20256 e functional description data sheet 60 04.2001 ? figure 4-7 descriptor structure although the data management unit works 32-bit oriented, it is possible to begin a transmit data section at an uneven address. the two least significant bits of the transmit data pointer determine the beginning of the data section and the number of bytes in the first dword of the data section, respectively. in receive direction the address of the data sections must be dword aligned. 4.3.2 receive descriptor each receive descriptor is initialized by the host cpu and stored in system memory as part of a linked list. the munich256 reads a descriptor, when requested to do s o from the host by a receive command or after branching from one receive descriptor to the next receive descriptor. each receive descriptor contains four dwords, where the first three dwords contain link and packet information and the last dword contains status information. once the descriptor is processed the status information will be written back to system memory by the munich256 (receive status update). when the munich256 next descriptor pointer data pointer 0 1 0 2 08 h 08 h 0 1 0 0 0 0 0 0f h 0e h 0d h 0c h 13 h 12 h 11 h 10 h 14 h next descriptor pointer data pointer 0 0 0 1 10 h 09 h 1 1 0 0 0 0 0 next descriptor pointer data pointer 0 0 0 0 0c h 0c h 0 1 0 0 0 0 0 0f h 0e h 0d h 0c h 13 h 12 h 11 h 10 h 14 h flag crc crc 7e h flag crc payload linked list in system memory in little endian mode data on serial link 03 h 02 h 01 h 00 h 07 h 06 h 05 h 04 h 0b h 08 h 09 h 0a h 03 h 02 h 01 h 00 h 07 h 06 h 05 h 04 h 0b h 08 h 09 h 0a h 7e h peb 20256 e pef 20256 e functional description data sheet 61 04.2001 branches to a new descriptor it reads the link and packet information entirely and stores it in its on-chip channel database. table 4-2 receive descriptor structure hold hold indication hold indicates that a descriptor is the last element of a linked list containing valid information. 0 next descriptor is available in the shared memory. after checking the hold bit the data management unit branches to the next receive descriptor. 1 this descriptor is the last one that is available for a channel. this means that the data section where this descriptor points to is the last data section which is available for data storage. after processing of descriptor has finished, the data management unit repolls the descriptor one time to check if hold has already been cleared. if hold is still set the corresponding receive channel is deactivated as long as the system cpu does not request a new activation via a ?receive hold reset? command or forces the munich256 to branch to a new linked list via a ?receive abort/branch? command. note: when repolling a descriptor the munich256 checks the hold bit and the bit field nextreceivedescriptorpointer. all other information are not updated in the internal channel database. dword addr. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 h 0 hold rhi offset(2:0) 0 0 0 0 descriptorid(5:0) 04 h nextreceivedescriptorpointer(31:2) 08 h receivedatapointer(31:2) 0c h fe c 0 0 0 0 0 0 0 0 0 mfl rfod crc ilen rab dword addr. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 h no(15:0) 04 h nextreceivedescriptorpointer(31:2) 0 0 08 h receivedatapointer(31:2) 0 0 0c h bno(15:0) peb 20256 e pef 20256 e functional description data sheet 62 04.2001 rhi receive host initiated interrupt this bit indicates that the munich256 shall generate a ?receive host initiated? interrupt vector after it has finished processing the descriptor. 0 data management unit does not generate an interrupt vector after it has processed the receive descriptor. 1 data management unit generates an interrupt vector, as soon as all data bytes are transferred into the current data section and the status information is updated. offset offset of unused data section. this bit field allows to reserve memory space in increments of dwords for an additional header. if the marked descriptor is the first one of a new packet the data management unit will write data at the address receivedatapointer+4xoffset. note: offset x 4 must be smaller than no. note: this option is not available in transparent mode. descriptorid this bit field is read by the data management unit and written back in the corresponding interrupt status of a channel interrupt vector which is generated by the data management unit. this value provides a link between the descriptor and the corresponding interrupt vector. no byte number this bit field defines the size of the receive data section allocated by the host. the maximum buffer length is 65535 bytes and it has to be a multiple of 4 bytes. data bytes are stored in the receive data section according to the selected mode (little endian or big endian). note: please note that the device handles the status (crc, flag and frame status) of frame based protocols (hdlc, ppp) internally in the same way as payload data. therefore byte number should include four bytes more than the maximum length of incoming frames. nevertheless, the frame status will be deleted from the end of the data stream and be attached as a status word to the receive descriptor. the frame status will not be written to the data section. peb 20256 e pef 20256 e functional description data sheet 63 04.2001 nextreceivedescriptorpointer this pointer contains the start address of the next valid receive descriptor. after completion of the current receive descriptor the data management unit branches to the next receive descriptor to continue data reception. system cpu can force the munich256 to branch to the beginning of a new linked list via the command ?receive abort/branch?. in this case the receive descriptor address provided via register cspec_frda is used as the next receive descriptor pointer to be branched to. receivedatapointer this pointer contains the start address of the receive data section. the start address must be dword aligned. fe frame end it indicates that the current receive data section (addressed by receivedatapointer) contains the end of a frame. this bit is set by the data management unit after transferring the last data of a frame from the internal receive buffer into the receive data section which is located in the shared memory. moreover the bit field bno and the status bits are updated, the complete (c) bit is set and a ?frame end? interrupt vector is generated. c complete this bit indicates that ? filling the data section has completed (with or without errors), ? processing of this descriptor was aborted by a ?receive abort/branch? command, ? or the end of frame (ppp, hdlc) was stored in the receive data section. the complete bit releases the descriptor. bno byte number of received data the data management unit writes the number of data bytes stored in the current data section into bit field bno. peb 20256 e pef 20256 e functional description data sheet 64 04.2001 when the munich256 completes a data section, which included the end of a frame (cbit and fe bit are set), or when the munich256 branches to a new linked list due to a 'receive abort/branch' command the status information bits rab, ilen, crc, rfod and mfl are updated as part of the receive status update. in the abort scenario, the c bit will always be set. bit fe will be set only, if the particular channel operates in hdlc or ppp mode. rab receive abort this bit is set when ? the incoming serial data stream contained an abort sequence, or ? an incoming frame was aborted by the command ?receive abort/ branch?, or ? when a channel is switched off while a frame is being received. ilen illegal length this bit is set, when the length of the incoming data packet was not a multiple of eight bits. crc crc error this bit is set, when the checksum of an incoming data packet was different to the internally calculated checksum. rfod receive frame overflow this bit is set, when a receive buffer overflow occurred during data reception. mfl maximum frame length this bit is set, when the length of the incoming data packet exceeded the value programmed in conf1.mfl. 4.3.3 data management unit receive the data management unit receive transfers data for each of the 256 logical receive channels from the internal receive buffer to the data sections of the corresponding channel. to fulfill the task it has to be initialized for operation, which is described in ? channel programming / reprogramming concept ? on page115 . relevant part of the channel information for the data management unit is the address pointer to the first receive descriptor, the channel interrupt queue and the channel interrupt mask. the first receive descriptor of a channel is fetched from system memory and stored in the chip internal channel database the first time the receive buffer requests a data transfer for the channel. the descriptor contains a pointer to the data section, the size of the provided data section and a pointer to the next receive descriptor. the data transfer is requested as soon as a programmed receive buffer threshold is reached. this threshold is programmed during channel setup on a per channel basis. task of the data management unit is to calculate the maximum number of bytes that can peb 20256 e pef 20256 e functional description data sheet 65 04.2001 be stored in the receive data section and to compare this with the length of the requested data transfer. in case that the requested transfer length from the receive buffer fits into the provided data section the data management unit transfers the data block to system memory in one single burst. if the requested transfer length exceeds the available space of the data section the transfer is divided into two or more parts. data packets are written to the data section until the given data section is filled or the end of a packet is reached. if the data section in the shared memory is completely filled with data, the data management unit updates the status word of the receive descriptor by setting the complete (c) bit and the number of bytes (bno), which are stored in the data section. in this case the number of bytes written to the data section equals the size of the data section. if the data packet, which is written to system memory, contains the remaining part of a completely received packet, the data management unit updates the status word of the receive descriptor by setting the complete bit together with the frame end (fe) bit. the bno field is updated on the actual value of bytes written to the data section. if enabled, the data management unit generates a ?frame end? channel interrupt vector. with the next receive buffer request the data management unit branches to the next receive descriptor, which was referenced in the next descriptor field of the current processed descriptor. to keep track of the linked list the data management unit provides the possibility to issue a ?receive host initiated? interrupt vector, which is generated after the status word was updated. to enable this interrupt vector the bit rhi must be set in a descriptor. descriptor hold operation processing of the descriptor list is controlled by the hold bit, which is located in the first dword of each receive descriptor. the hold bit indicates that the marked descriptor is the last descriptor containing a valid data buffer. the data management unit will not branch to a next descriptor until the hold condition is removed or a ?receive abort? command forces the munich256 to branch to the beginning of a new linked list. since the hold bit marks the last descriptor in a linked list, it may prevent that further received data packets can be written to system memory. when a given data section is filled, and d oes not contain the end of a frame (frame based protocols) and the requested transfer length could not be satisfied, the data management unit polls the hold bit of the current receive descriptor once more. if the hold bit is removed, it branches to the next descriptor. when the hold bit is still ?1?, an internal poll bit is set and the data management unit does not branch to the next descriptor. additionally a ?hold caused receive abort? interrupt vector is generated. the status of the descriptor in the shared memory is aborted (rab bit set) and the complete bit and the frame end bit are set in the receive descriptor. the rest of the frame will be discarded. as long as the hold bit remains set further data of the same channel is peb 20256 e pef 20256 e functional description data sheet 66 04.2001 discarded and for each discarded frame a ?silent discard? interrupt vector with the bits hrab and rab set is generated. if the current data section was filled and does contain the end of frame a ?frame end? interrupt vector is generated and the descriptor is updated on the fe bit and the c bit. therefore the status of this receive descriptor is error free. with the next request of the receive buffer, the data management unit repolls the hold bit of the current receive descriptor. if the hold bit is removed, it branches to the next descriptor. if the hold bit is still ?1?, an internal poll bit is set. as long as the hold bit remains set, further data of the same channel is discarded and for each discarded frame a ?silent discard? interrupt vector with bits hrab and rab set is generated. when the receive buffer request matches exactly the remaining size of the data section and the data block does not contain the end of a packet, it is stored completely in the data section. the descriptor is updated immediately (c bit set). with the next receive buffer request, the data management unit repolls the hold bit of the current receive descriptor. if the hold bit is removed, it branches to the next descriptor. if the hold bit is still ?1?, an internal poll bit is set. additionally a ?hold caused receive abort? interrupt vector is generated and the rest of the frame is discarded. as long as the hold bit remains set further data of the same channel is discarded and for each discarded frame a ?silent discard? interrupt vector is generated. the system cpu can remove the hold condition, when the next receive descriptor is available in shared memory. therefore the cpu has to execute a ?receive hold reset? command, which will reactivate the channel. when the receive buffer requests a new data transfer, the data management unit will repoll the last receive descriptor. if the hold bit was removed, the data management unit branches to the next receive descriptor pointed to by bit field nextreceivedescriptor. note: in protocol modes hdlc and ppp data from receive buffer is discarded until the end of a received frame is reached. as soon as the beginning of a new frame is received, the data management unit starts to fill the data section. note: in transparent mode data transferred from receive buffer is written immediately to the data section of the next receive descriptor. if the cpu issues a ?receive hold reset? command and does not remove the hold bit (erroneous programming), no action will take place. 4.3.4 transmit descriptor the transmit descriptor in shared memory is initialized by the host cpu and is read afterwards by the munich256. the address pointer to the first transmit descriptor is stored in the on-chip channel database, when requested to do so by the host cpu via the ?transmit init? command. the first three dwords of a transmit descriptor are read when the transmit buffer requests a data transfer for this channel and then they are stored in the on-chip memory. also they are read when branching from one transmit peb 20256 e pef 20256 e functional description data sheet 67 04.2001 descriptor to the next transmit descriptor. therefore all information in the next descriptor must be valid when the data management unit branches to a descriptor. the last dword of a transmit descriptor optionally is written by the munich256 when processing of a descriptor has finished. table 4-3 transmit descriptor structure fe frame end it indicates that the current transmit data section (addressed by transmit data pointer) contains the end of a frame. after the last byte is read from system memory this bit is passed to the transmit buffer and to the protocol machine. the bit fe informs the transmit buffer to move a stored frame to the protocol machine even if the programmed transmit forward threshold is not reached (see ? internal transmit buffer ? on page74 ). the protocol machine is informed to append the checksum (hdlc, ppp) and then to send the interframe time-fill. providing a transmit descriptor with fe = ?0? and hold = ?1? is an error. hold hold indication it indicates that this descriptor is the last valid element of a linked list. 0 next descriptor is available in the shared memory. the data management unit branches to the next descriptor as soon as processing of the current descriptor has finished. 1 the current descriptor is the last descriptor containing valid data in the data section. as soon as the data management unit has transferred the data contained in the data section to the internal buffer, it tries one more time to read the descriptor. in case that dword addr. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 h fe hold thi cen 0 0 0 0 0 0 descriptorid(5:0) 04 h nexttransmitdescriptorpointer(31:2) 08 h transmitdatapointer(31:0) 0c h 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dword addr. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 h no(15:0) 04 h nexttransmitdescriptorpointer(31:2) 0 0 08 h transmitdatapointer(31:0) 0c h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 peb 20256 e pef 20256 e functional description data sheet 68 04.2001 the hold indication is still set, it stores further requests of the receive buffer in its channel database. the channel can be reactivated by issuing a ?transmit hold reset? command or by providing a new linked list via the ?transmit abort/branch? command, in which case not served requests are processed. note: when repolling a descriptor the munich256 checks the hold bit and the bit field nexttransmitdescriptorpointer. all other information are not updated in the internal channel database. no byte number the byte number defines the number of bytes stored in the data section to be transmitted. thus the maximum length of data buffer is 65535 bytes. in order to provide dummy transmit descriptors no = 0 is allowed in conjunction with the fe bit set. in this case (no = 0) a ?transmit host initiated? interrupt vector and/or the c-bit will be generated/set when the data management unit recognizes this condition. it is an error to set no=0 without fe bit set. thi transmit host initiated interrupt this bit indicates that the munich256 shall generate a ?transmit host initiated? interrupt vector after it has finished operating on the descriptor. 0 data management unit does not generate an interrupt vector after it has processed the transmit descriptor. 1 data management unit generates an interrupt vector, as soon as all data bytes are transferred to the internal transmit buffer and the status information is updated. descriptorid this bit field is read by the data management unit and written back in the corresponding interrupt status of a channel interrupt vector which is generated by data management unit. this value provides a link between the descriptor and the corresponding interrupt vector. nexttransmitdescriptorpointer this pointer contains the start address of the next transmit descriptor. it has to be dword aligned. after sending the indicated number of data bytes, the data management unit branches to the next transmit descriptor. the transmit descriptor is read entirely at the beginning of transmission and stored in on-chip memory. therefore all informations in the descriptor must be valid. system cpu can force the munich256 to branch to the beginning of a new linked list via the command ?transmit abort/branch?. in this case the transmit descriptor address provided via register cspec_ftda is used as the next transmit descriptor pointer to be branched to. peb 20256 e pef 20256 e functional description data sheet 69 04.2001 transmitdatapointer this 32-bit pointer contains the start address of the transmit data section. although the data management unit works dword oriented, it is possible to begin transmit data section at byte addresses. cen complete enable this bit is set by the cpu if the complete bit mechanism is desired: 0 the data management unit will not update the transmit descriptor with the c bit. in this mode the use of the thi interrupt is recommended. 1 the data management unit will set the c bit. c complete this bit is set by the data management unit, when the bit cen of a descriptor is set and when it ? completed reading a data section normally, or ? it was aborted by a ?transmit off? command or by a ?transmit abort/ branch? command . the complete bit releases the descriptor. 4.3.5 data management unit transmit the data management unit transmit provides the interface between system memory on one side and the internal transmit buffer on the other side. the data management unit handles requests of the transmit buffer, controls the address and burst length calculation, initiates data transfers from system memory to the transmit buffer and handles the linked lists on a per channel basis. for initialization the cpu programs the first transmit descriptor address, the interrupt mask, the interrupt queue and starts the channel with the ?transmit init? command. for detailed description of channel commands refer to ? channel commands ? on page116 .the data management unit then fetches the given information and stores them in its on-chip channel database. the first transmit descriptor is fetched from system memory and stored in the chip internal channel database the first time the transmit buffer requests data for a channel. it contains a pointer to the data buffer, the length of the data section as well as a pointer to the next transmit descriptor. after the first descriptor is stored internally a ?transmit command complete? interrupt vector is generated. data transfers are requested as long as the number of empty locations is below a programmable refill threshold. the number of empty locations is reported from the transmit buffer to the data management unit. task of the data management unit is to calculate the number of bytes that can be loaded from the data section based on the no peb 20256 e pef 20256 e functional description data sheet 70 04.2001 field of the transmit descriptor and to compare this with the number of bytes requested by the transmit buffer. depending on the bit field no in the transmit descriptor several read accesses must be performed by the data management unit. it stops serving the request as soon as the requested amount of data was transferred to the transmit buffer, when a frame end bit (fe) in the processed transmit descriptor is set or when the channel was aborted using a ?transmit abort? command. serving the request can also be suspended, when the programmed transmit burst length (conf3.tpbl) is reached. all these events may result in open transmit buffer locations, but the data management unit stores this information as open requests in the channel database and processes these requests continuously. the data management unit alternately serves requests issued by the transmit buffer or open requests stored in its internal channel database. if there are open requests for a channel, data transmission will be initiated. the procedure is the same as described above. it stops, if the requested amount of data is served or when the fe bit field is set. if a transmit descriptor has its fe bit set and all data of the data section is moved to the transmit buffer, the data management unit serves requests of further channels or looks for open requests in its database. therefore open requests from other channels are served faster and possible underruns can be avoided. the next transmit descriptor will be retrieved with the next data transfer of the channel. when the data management unit completed reading a data section associated with a transmit descriptor, it updates the complete (c) bit in the status word of the transmit descriptor if the complete enable (cen) bit is set. additionally a ?transmit host initiated? interrupt vector is generated if the thi bit is set in the transmit descriptor. afterwards the data management unit the munich256 branches to the next transmit descriptor. descriptor hold operation the data transfer is controlled by the hold bit, which is located in the first dword of a transmit descriptor. the hold bit indicates that the marked descriptor is the last descriptor in a linked list. the data management unit will not branch to the next descriptor until the hold condition is removed or a ?transmit abort? command forces the munich256 to branch to a new linked list. if the hold bit and the frame end bit are set together in a descriptor, the data management unit transfers all data of the belonging data section to the transmit buffer and optionally sets the c-bit in the current transmit descriptor. when a new data transfer is requested (either from the transmit buffer or an open request) the data management unit repolls the descriptor. if the hold bit is removed, it will branch to the next transmit descriptor. if the hold bit is still set, that channel is suspended for further operation. following requests from the transmit buffer will not be served, but the number of requested data is stored in the open request registers. peb 20256 e pef 20256 e functional description data sheet 71 04.2001 if the hold bit is detected in a descriptor and the frame end bit is not set, the data management unit will transfer all data of the belonging data section to the transmit buffer. afterwards it generates a ?hold caused transmit abort? interrupt vector in order to inform the host cpu about the erroneous descriptor structure. in ppp and hdlc mode the abort status is propagated to the transmit buffer and the protocol machine, so that a abort sequence is sent on the serial side. in tma mode the data management unit generates a ?hold caused transmit abort? interrupt vector every time it recognizes the hold bit. then it reads the transmit descriptor once more. if the hold bit is removed it branches to the next transmit descriptor and proceeds with normal operation. otherwise, when the hold bit is still set, the channel is suspended for further operation and an internal poll bit is set. following requests from the transmit buffer will not be served, but the number of requested data is stored in the open request register. the host cpu can remove the hold condition, when the next transmit descriptor is available in system memory. therefore the cpu has to execute a ?transmit hold reset? command, which will reactive the channel. when the transmit buffer requests a new data transfer or when open request are stored in the on-chip database the data management unit repolls the transmit descriptor and checks the hold bit again. if the hold bit is removed it branches to next transmit descriptor. if the cpu issues a ?transmit hold reset? command and does not remove the hold bit (erroneous programming), no action will take place. nevertheless, the cpu always has to issue a ?transmit hold reset? command when it removes the hold bit in a descriptor, no matter the data management unit has already seen the hold bit or not. 4.3.6 byte swapping the munich256 operates per default as a little endian device. to support integration into big endian environments, the data management unit provides an internal byte swapping mechanism, which can be enabled via bit conf1.lbe. the big endian swapping applies only to the data section pointed to by the receive and transmit descriptors in the shared memory. note: byte swapping only effects the organization of packet data in system memory. all internal registers, as well as the descriptors, address pointers or interrupt vectors are handled with little endian byte ordering. peb 20256 e pef 20256 e functional description data sheet 72 04.2001 table 4-4 example for little/big endian with bno = 3 table 4-5 example for little big endian with bno = 7 4.3.7 transmission bit/byte ordering data is transmitted beginning with byte zero in increasing order. vice versa data received is stored starting with byte zero. the position of byte zero depends on the selected endian mode. each byte itself consists of eight bits starting with bit zero (lsb) up to bit seven (msb). data on the serial line is transmitted starting with the lsb. the first bit received is stored in bit zero. 4.4 buffer management 4.4.1 internal receive buffer the internal receive buffer provides buffering of frame data and status between the protocol handler and the receive data management units. internal buffers are essential to avoid data loss due to the pci bus latency, especially in the presence of multiple devices on the same pci bus, and to enable a minimized bus utilization through burst accesses. the incoming data from the protocol handler is stored in a receive central buffer shared by all the 256 channels. the buffer is written by the protocol handler every time a complete dword is ready or the last byte of a frame has been received. each channel has an individual programmable threshold code, which determines after how many dwords a data transfer into the shared memory is generated. the threshold therefore defines the maximum burst length for a particular channel in receive direction. a data transfer is also requested as soon as a frame end has been reached. programming the burst length to be greater than 1 dword avoids too frequent accesses to the pci bus, thereby optimizing use of this resource. for real time channels with lowest possible latency (example: constant bit rate) a value of one dword can be selected for the burst length. bno little endian big endian 3 - byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 - bno little endian big endian 7 byte3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte3 - byte 6 byte 5 byte 4 byte 4 byte 5 byte 6 - peb 20256 e pef 20256 e functional description data sheet 73 04.2001 the total size of the internal receive buffer is 12 kbyte. if all the 256 channels are active, the average burst threshold should be programmed with 8 dwords, so that 4 dwords are available on the average to compensate for pci latency and avoid data loss. however if less than 256 channels are active or if only 64 kbit/s channels are used, the burst threshold may be programmed to a higher value. in other words, the sum of all channel thresholds shall not exceed the maximum receive buffer locations. in order to prevent an overload condition from one particular channel (e.g. receiving only small or invalid frames), the receive buffer provides the capability to delete frames which are smaller or equal than a programmable threshold. all frames that have been dropped will be counted and an interrupt vector will be generated as soon as a programmable threshold has been reached. the actual value of the counter can be read in the small frame dropped counter register. peb 20256 e pef 20256 e functional description data sheet 74 04.2001 ? figure 4-8 receive buffer thresholds for performance monitoring the receive buffer provides the capability to monitor the receive buffer utilization and to generate interrupts when certain fill thresholds have been reached. 4.4.2 internal transmit buffer the internal transmit buffer with a total size of 32 kbyte stores protocol data before it is processed by the protocol machine. the transmit buffer is essential to ensure that enough data is available during transmission, since pci latency and usage of multiple minimum frame length receive burst threshold receive burst threshold data management unit receive buffer frame protocol machine minimum frame length receive burst threshold receive buffer protocol machine data management unit 1 st burst 2 nd burst frame delete example b: drop of small frames example a: normal operation peb 20256 e pef 20256 e functional description data sheet 75 04.2001 channels limit access to system memory for a particular channel. a programmable transmit buffer size and two programmable threshold are configurable by the host cpu for each channel. note: the sum of both thresholds must be smaller than the transmit buffer size of a particular channel. ? figure 4-9 transmit buffer thresholds the threshold values have the following effect: ? data belonging to one channel stored in the internal transmit buffer will only be transferred to the protocol machine when the transmit forward threshold is reached or if a complete frame is stored inside the transmit buffer. this mechanism avoids data underrun conditions. transmit forward threshold transmit refill threshold data management unit transmit buffer protocol machine frame wait with data trans- mission until buffer level reaches transmit forward threshold request new data as long as number of empty locations is above transmit refill threshold programmable number of buffer locations per channel peb 20256 e pef 20256 e functional description data sheet 76 04.2001 ? as long as the amount of data stored in the transmit buffer is below the transmit refill threshold the data management unit will keep filling the buffer by initiating pci burst transfers. note: since there is a delay between the time the transmit buffer requests data from the data management unit and the time the data management unit serves the request, the actual number of empty locations may be higher than the transmit refill threshold. to determine the maximum pci burst length an additional parameter is available which limits these requests up to a maximum of 64 dwords. 4.5 protocol description the protocol machines provide protocol handling for up to 256 channels. the protocol machines implement 4 modes, which can be programmed independently for each channel: hdlc, bit-synchronous ppp, octet-synchronous ppp and transparent mode a. the configuration of each logical channel is programmed via the pci bus and will be stored inside the protocol machines. furthermore the current state for the protocol processing (crc check, 1 bit count,...) is also stored inside the protocol machines. each protocol machine (receive, transmit) handles a maximum of 256 channels and a maximum aggregate bit rate of up to 90 mbit/s. 4.5.1 hdlc mode ? figure 4-10 hdlc frame format the frame begin and frame end synchronization is performed with the flag character 7e h . shared opening and closing flag is supported in receive direction and can be programmed in the channel configuration register for transmit direction. shared ?0? bit between two flags is only supported in receive direction. interframe time-fill can be programmed to either flag 7e h or ff h indicating idle. in receive operation, prior to frame check sum (fcs) computation, any ?0? bit that directly follows five contiguous ?1? bits is discarded. when closing flag is recognized, a crc check, octet boundary check, mfl (maximum frame length) check, a short frame check and an additional small frame check are performed. short frames have less than 4 octets if crc16 is used or less than 6 octets if crc32 is used. an aborted frame is recognized if 7 or more ?1?s are received. in transmit operation after the crc computation a ?0? bit is inserted after every sequence of five contiguous ?1? bits. when frame end is indicated in the belonging transmit descriptor the calculated crc is transmitted and a flag is generated. if an underrun flag 0111 1110 address 8 bits control 8 bits information <=0 bits crc 16/32 bits flag 0111 1110 peb 20256 e pef 20256 e functional description data sheet 77 04.2001 occurs in the internal transmit buffer (because of pci latency e.g.) an abort sequence with 7 ?1?s is transmitted and an underrun interrupt is generated. the abort sequence is also generated if the host cpu resets or aborts a channel during the transmission of a frame. an invert option is provided to invert all the data output or data input between serial line and protocol machines or vice versa. the following crc modes are supported: ? 16 bit crc 1+x 5 +x 12 +x 16 ? 32 bit crc 1+x+x 2 +x 4 +x 5 +x 7 +x 8 +x 10 +x 11 +x 12 +x 16 +x 22 +x 23 +x 26 +x 32 optionally crc transfer and check can be disabled. 4.5.2 bit synchronous ppp with hdlc framing structure ? figure 4-11 bit synchronous ppp with hdlc framing structure same as hdlc. the handling of the abort sequence differs from that in hdlc mode. if 7e h is programmed as interframe time fill character, the abort sequence consists of 7 ?1?s. if ff h is programmed as interframe time fill character, the abort sequence consists of 15 ?1?s. the same programmable parameters as in hdlc mode apply to bit synchronous ppp. 4.5.3 octet synchronous ppp this mode uses a frame structure similar to the bit synchronous ppp mode. the frame begin and end synchronization is performed with the flag character (7e h ). use of a shared opening and closing flag is supported if programmed in the channel configuration register. use of a shared ?0? bit between two flags is not supported. a 16 or 32 bit crc is computed over all service data read from the transmit buffer and appended to the end of the frame. the octet synchronous ppp mode uses octet stuffing instead of ?0? bit stuffing in order to replace control characters used by intervening hardware equipment. this allows transparent transmission and also recognition and removal of spurious characters inserted by such equipment. a 32 bit per channel asynchronous control character map (accm) specifies characters in the range 00 h -1f h to be stuffed/destuffed in service data and fcs field. in addition, the del control character (7f h ) a nd any of 4 accm extension characters stored in a programmable 32 bit register can be selected for character stuffing/destuffing. when a flag 0111 1110 address 1111 1111 control 0000 0011 protocol 8/16 bits information padding fcs 16/32 bits flag 0111 1110 peb 20256 e pef 20256 e functional description data sheet 78 04.2001 character specified to be mapped is found in service data or the fcs field, it is replaced by a 2 octet sequence consisting of 7d h ( control escape) followed by the character exored with 20 h (e.g. 13 h is mapped to 7d h 33 h ). in addition to the per channel specification of characters to be mapped, the control escape sequence 7d h and 7e h in the service data stream are always mapped. opening and closing flags are not affected. the abort sequence consists of the control escape character followed by a flag character 7e h (not stuffed). between two frames, the interframe time fill character is always 7e h . if in the transmit direction a data underrun occurs during transmission of a frame and the frame has not finished, an abort sequence is automatically sent (escape character followed by a flag) and an underrun interrupt vector will generated. if the transmit buffer indicates an empty condition for a channel between two frames (idle or interframe fill), the protocol machine will continue to send interframe time fill characters. also an abort sequence will be generated if a channel is reset or an abort command is issued during transmission of a frame. the following crc modes are supported: ? 16 bit crc 1+x 5 +x 12 +x 16 ? 32 bit crc 1+x+x 2 +x 4 +x 5 +x 7 +x 8 +x 10 +x 11 +x 12 +x 16 +x 22 +x 23 +x 26 +x 32 crc computation/check or removing can be disabled. 4.5.4 transparent mode when programmed in transparent mode, the protocol machine performs fully transparent data transmission/reception without hdlc framing, i.e. without ? flag insertion/removing ? crc generation/crc check ? bit stuffing/destuffing (0 bit insertion/removal). an option ?transparent mode pack? is provided to support subchanneling. if subchanneling is used (logical channels of less than 64 kbit/s), masked bits in the protocol data are set high and each bit in shared memory maps directly to enabled (not masked) bits on the serial line. otherwise they contain protocol data, that is each byte in shared memory maps directly to a time slot. a programmable transparent flag can be programmed which will be inserted between payload data or is removed during reception of a payload data. an invert option is provided to invert the outgoing or incoming data stream. 4.6 mailbox the munich256 contains a mailbox to allow communication between two intelligent peripherals connected to the pci bus and the local microprocessor bus. the mailbox is organized in two pages of eight registers. the first page is used to store information from peb 20256 e pef 20256 e functional description data sheet 79 04.2001 the pci side and to read the information from the local microprocessor side. the second page is used for the opposite direction, from the local microprocessor side to the pci side. each page consists of one status register and seven data registers. the mailbox provides a ?doorbell? capability. in this case an interrupt vector can be generated to inform the addressed intelligent peripheral that new information has been stored in the mailbox. this interrupt vector will be generated on write accesses to the status register of the selected page. as an example , consider when the pci host system wants to transfer data to an intelligent peripheral. first it loads data into the mailbox data registers mbp2e1 through mbp2e7, and then writes a status information to the mailbox status register mbp2e0. this last action causes an interrupt vector to be written to the interrupt fifo which is connected to the local bus. the presence of an interrupt vector results in assertion of pin lint . the intelligent peripheral recognizes the interrupt pin asserted and reads the interrupt vector out of the interrupt fifo (which results in deassertion of pin lint ), and then reads data from the mailbox data registers. ? figure 4-12 mailbox structure alternately , consider when an intelligent peripheral connected to the local bus wants to transfer data to the pci host system. first it loads data into the mailbox data registers mbe2p1 through mbe2p7 and then it writes status information to the mailbox status register mbe2p0. this causes a system interrupt vector to be written to the pci host system, indicating that valid data is contained in the mailbox data registers. mailbox registers pci --> local bus interrupt controller local bus interrupt controller pci side mbe2p1..mbe2p7 mbp2e0 mbe2p0 pci interface local bus interface mbp2e1..mbp2e7 mailbox registers local bus --> pci configuration bus i configuration bus ii interrupt vector interrupt vector lint inta read only read only peb 20256 e pef 20256 e functional description data sheet 80 04.2001 this interrupt vector will be written to the interrupt queue specified in conf1.sysq and together with this the pin inta will be asserted. the processor sees the interrupt pin asserted, reads the register gista in order to determine the interrupt queue, and then writes a ?1? to the interrupt status acknowledge register giack to clear the interrupt. next, it reads the interrupt vector which contains a copy of the mailbox status register and then reads the mailbox data registers. 4.7 interrupt controller all layer two interrupts (channel, port, system and command interrupts) are handled via an internal interrupt controller which forwards those interrupts to external interrupt queues. this interrupt controller is connected to the pci interrupt pin inta . mailbox interrupts are handled via an internal interrupt fifo which is connected to the local bus interrupt pin lint (normal operation). additionally the interrupts stored in the internal interrupt fifo can be notified via the pci interrupt pin inta . the munich256 also provides the capability to bridge the local bus interrupt lint to the pci bus. 4.7.1 layer two interrupts all channel interrupts, port interrupts and system interrupts are written in form of interrupt vectors to interrupt queues. each interrupt vector has an interrupt source. an interrupt source is either a channel, the port handler or certain device functions (system interrupts). after reset no interrupt vector is generated since port and system interrupts are masked and channels are in their idle state. each interrupt source forwards its interrupt vector to the interrupt controller, together with the information in which interrupt queue the vector should be forwarded. the interrupt controller moves the interrupt vector to the selected interrupt queue. channel interrupts can optionally be forwarded to a dedicated high priority interrupt queue (interrupt queue seven). a programmable interrupt queue high priority mask determines channel interrupts, which shall be forwarded into the high priority interrupt queue instead of queueing them in the selected interrupt queue. this function is available for each interrupt queue and allows to queue important interrupt conditions in the high priority queue. peb 20256 e pef 20256 e functional description data sheet 81 04.2001 ? figure 4-13 layer two interrupts (channel, command, port and system interrupts as soon as the interrupt controller has written an interrupt vector to one of the nine interrupt queues the pci interrupt pin inta is asserted. the global interrupt status register indicates in which interrupt queue the interrupt vector can be found. each of the pci interface system memory system interrupts channel, command interrupts interrupt controller interrupt queue interrupt status: gista, gmask interrupt queue setup: iqia, iqba, iql, iqmask 00000000 h ffffffff h iqba iv pci bus interrupt bus port interrupts int. vector setup: conf1, conf2 1 256 int. vector setup: cspec_ivmask, cspec_buffer int. vector setup: pmr, conf2 1 2 3 4 microprocessor 1 . interrupt source forwards interrupt vector to interrupt controller. 2. interrupt controller moves interrupt vector to interrupt queue. 3. interrupt controller asserts inta (if enabled). 4. microprocessor reads status register gista. 5. microprocessor reads interrupt queue . inta 5 from layer one interrupt fifo lint peb 20256 e pef 20256 e functional description data sheet 82 04.2001 nine interrupt queues can be masked. in this case the interrupt pin inta is not asserted, but the interrupt vector is still written into the assigned interrupt queue. an interrupt queues is a reserved memory locations in system memory. the munich256 supports up to eight interrupt queues which are organized in form of ring buffers with a programmable start address and a programmable size per interrupt queue. additionally there is one fixed sized command interrupt queue where command interrupts are stored. the size of this queue is two times 256 dwords ( figure 4-14 ). ? figure 4-14 interrupt queue structure in system memory 4.7.1.1 general interrupt vector structure each interrupt vector is 32 bit wide and contains several subfields, which indicate the interrupt group and depend on the interrupt group the interrupt information. bit 31 of the interrupt vector is generally set to ?1? by the munich256 and allows the system cpu to clear the bit in order to mark processed interrupts. table 4-6 interrupt vector structure 31 30 29 28 27 26 24 23 16 1 type(1:0) stype(1:0) queue(2:0) int(23:0) 15 0 int(23:0) ring buffer channel 255: transmit command iv channel 0: transmit command iv channel 255: receive command iv channel 0: receive command iv interrupt vector 1 interrupt vector 2 interrupt vector 3 interrupt vector iql*16 channel, port and system interrupt queue command interrupt queue iqba note: iv = interrupt vector iqba+4 h iqba iqba+4 h channel 1: receive command iv peb 20256 e pef 20256 e functional description data sheet 83 04.2001 type interrupt type the interrupt vectors are divided into four basic groups, where type determines the interrupt group. a further classification of interrupts is done with the subtype indication. 00 b command interrupts 01 b channel interrupts 10 b port interrupts 11 b system interrupts stype interrupt subtype a specific interrupt type is divided into several subtypes. in general stype(1) indicates the data path (transmit, receive) generating the interrupt. queue interrupt queue the interrupt vectors are written into 9 external interrupt queues located in the shared memory. corresponding to these 9 queues are 9 interrupt queue start addresses and 8 interrupt queue length registers, since the interrupt queue 8 has a fixed length of 2 x 256). int interrupt information int itself contains the interrupt information. the meaning of int is dependent on type and stype indication. peb 20256 e pef 20256 e functional description data sheet 84 04.2001 4.7.1.2 system interrupts ? mb mailbox the ?mailbox? interrupt vector is generated, in case that the local microprocessor has written data to the mailbox status register mbe2p0. the bit field info contains a copy of mbe2p0. rbaf receive buffer access failed the ?receive buffer access failed? interrupt vector is generated, when the protocol machine discarded packets due to permanent inaccessibility of the receive buffer. this interrupt is issued as soon as the programmable threshold stored in register rbaft is reached. the actual value of discarded packets is stored in register rbafc. rbew receive buffer queue early warning the ?receive buffer queue early warning? interrupt vector is generated, when the receive buffer data threshold has been exceeded (rbth.rbth). this interrupt can be masked via bit conf1.rbim. raew receive buffer action queue early warning the ?receive buffer action queue early warning? interrupt vector is generated, when the receive data action queue threshold (rbth.rbaqth) has been exceeded. the receive buffer action queue stores all requests of the receive buffer to forward data packets to system memory. this interrupt vector can be masked via bit conf1.rbim. pb pci access error the ?pci access error? interrupt vector is generated, when system software tries to read/write internal registers with accesses that do not enable all byte lanes, e.g. the access is not a full 32 bit access. the bit field info contains the register address which was tried to access. info contains additional interrupt information data according to the bit, which is set: see specific interrupt for details. 31 30 29 28 27 26 24 20 19 18 17 16 1 11 b 00 b queue(2:0) 0 0 0 mb rbf rbew raew pb 15 0 info(15:0) peb 20256 e pef 20256 e functional description data sheet 85 04.2001 4.7.1.3 port interrupts port interrupt vectors indicate the synchronous or asynchronous state of a port. immediately after enabling both, the port and the port interrupts, port interrupts are generated indicating the synchronous or asynchronous state of a port. after this initial interrupt vector generation, further interrupts are written only when the state of a port changes from synchronous state to asynchronous state or vice versa. port interrupts are enabled by resetting the corresponding mask bit in register pmr. transmit interrupts ? port port number this bit field identifies the port for which the information in the interrupt vector is valid. syn synchronization achieved port has changed from asynchronous state to synchronous state. this interrupt is available for ports configured in t1 or e1 , 4.096mhz mode or 8.192mhz mode. in unchannelized mode there is no synchronous state. a transmit port changes to the synchronous state if the number of bits between two synchronization pulses is equal to a multiple of the number of frame bits of the selected mode. the first synchronization pulse after a port is enabled causes the port to change to the synchronous state. asyn asynchronous state the transmitter generates an ?asynchronous state? interrupt vector if a port has changed from synchronous to asynchronous state. this interrupt is available for ports configured in t1 , e 1 , 4.096mhz mode or 8.192mhz mode. in unchannelized mode there is no asynchronous state. in general a port is in asynchronous state when a port is disabled. a port changes to the asynchronous state if the number of bits between two synchronization pulses is not equal to a multiple of the number of frame bits of the selected mode. 31 30 29 28 27 26 24 17 16 1 10 b 10 b queue(2:0) 0 0 0 0 0 0 syn asyn 15 5 4 0 0 0 0 0 0 0 0 0 0 0 0 port(4:0) peb 20256 e pef 20256 e functional description data sheet 86 04.2001 receive interrupts ? port port number this bit field identifies the port for which the information in the interrupt vector is valid. syn synchronization achieved port has changed from asynchronous state to synchronous state. this interrupt is available for ports configured in t1 , e 1 , 4.096mhz mode or 8.192mhz mode. in unchannelized mode there is no synchronous state. a receive port changes to the synchronous state if the number of bits between two synchronization pulses is equal to a multiple of the number of frame bits of the selected mode. the first synchronization pulse after a port is enabled causes the port to change to the synchronous state. asyn asynchronous state port has changed from synchronous to asynchronous state. this interrupt is available for ports configured in t1 or e1 , 4.096mhz mode or 8.192mhz mode. in unchannelized mode there is no asynchronous state. in general a port is in asynchronous state when a port is disabled. a port changes to the asynchronous state if the number of bits between two synchronization pulses is not equal to a multiple of the number of frame bits of the selected mode. 31 30 29 28 27 26 24 17 16 1 10 b 00 b queue(2:0) 0 0 0 0 0 0 syn asyn 15 4 0 0 0 0 0 0 0 0 0 0 0 0 port(4:0) peb 20256 e pef 20256 e functional description data sheet 87 04.2001 4.7.1.4 channel interrupts channel interrupt are divided into two subtypes: ? receive interrupt i and transmit interrupt i ? receive interrupt ii and transmit interrupt ii subtype i contains interrupts which indicate the general status of a channel. these interrupts are not linked to a descriptor. subtype ii contains interrupts which indicate a channel or packet status that is linked to a descriptor. each interrupt vector contains a descriptor id which can be used for tracking purposes. receive interrupt i ? rofp receive buffer overflow the ?receive buffer overflow? interrupt vector is generated, when one or more whole frames or short frames or changes of interframe time-fill (hldc, ppp) or data in general (tma) has been discarded due to the inaccessibility of the internal receive buffer. sf short frame detected the ?short frame detected? interrupt vector is generated, when the receiver detected a frame which length matches the condition defined in conf1.sfl. iffl interframe time-fill flag the ?interframe time-fill flag? interrupt vector is generated, when the receiver detected a interframe time-fill change from ff h to 7e h . ifid interframe time-fill idle the ?interframe time-fill idle? interrupt vector is generated, when the receiver detected a interframe time-fill change from 7e h to ff h . 31 30 29 28 27 26 24 1 01 b 00 b queue(2:0) 0 0 0 0 0 0 0 0 15 14 13 12 11 7 0 rofp sf iffl ifid sfd 0 0 0 chan(7:0) peb 20256 e pef 20256 e functional description data sheet 88 04.2001 sfd small frames dropped the ?small frames dropped? interrupt vector is generated, when the receiver discarded n small frames. the length of small frames is defined in conf3.minfl and the threshold value n is defined in register sfdt. chan channel number this bit field identifies the channel for which the information in the interrupt vector is valid. transmit interrupt i ? ur underrun the ?underrun? interrupt vector is generated, when the transmit buffer was not able to provide data to the protocol machine transmit. if this happens during transmission of a hdlc or ppp packet, the transmitter will end the already started data packet with an abort sequence. fe frame end the ?frame end? interrupt vector is generated, when one complete data packet has been transmitted via serial side. chan channel number this bit field identifies the channel for which the information in the interrupt vector is valid. 31 30 29 28 27 26 24 16 1 01 b 10 b queue(2:0) 0 0 0 0 0 0 0 0 15 14 7 0 ur fe 0 0 0 0 0 0 chan(7:0) peb 20256 e pef 20256 e functional description data sheet 89 04.2001 receive interrupt ii ? chan channel number this bit field identifies the channel for which the information in the interrupt vector is valid. rhi (receive) host initiated interrupt the ?(receive) host initiated? interrupt vector will be issued, if bit rhi is set in a receive descriptor and processing of this descriptor has finished. after receiving this interrupt vector, system software can release the descriptor, e.g. put the descriptor into a free pool. rab receive abort the ?receive abort? interrupt vector is generated, when an incoming data packet is aborted (more than 6 ?1? in case of hdlc or more than 15 ?1? in case of ppp) or if the receiver got a receive abort command from the system cpu. fe frame end the ?frame end? interrupt vector is generated, when one complete frame has been received completely and has been stored in system memory. hrab hold caused receive abort the ?hold caused receive abort? interrupt vector is generated, when the receiver discarded the first data packet after it has found a hold bit in a receive descriptor. rab, hrab silent discard the ?silent discard? interrupt vector (bit rab and hrab set together) occurs, if two or more frames have been discarded by the receiver due to continuous inaccessibility of receive descriptor. this occurs, if receive descriptor has hold bit set and receiver gets further data packets. the interrupt vector will be generated for each packet discarded. 31 30 29 28 27 26 24 23 22 21 16 1 01 b 01 b queue(2:0) 0 0 desid(5:0) 15 14 13 12 11 10 9 8 7 0 rhi rab fe hrab mfl rfod crc ilen chan(7:0) peb 20256 e pef 20256 e functional description data sheet 90 04.2001 mfl maximum frame length exceeded the ?maximum frame length exceeded? interrupt vector is generated, when the length of a received data packet exceeded the frame length defined in conf1.mfl. rfod receive frame overflow dma the ?receive frame overflow dma? interrupt indicates that protocol handler was unable to transfer data to the receive buffer. as soon as receive buffer can store data again, this interrupt is generated. crc crc error the ?crc error? interrupt vector is generated, when the internally calculated crc and the crc of a received packet did not match. ilen invalid length the ?invalid length? interrupt vector is generated, when the bit length of received frame was not divisible by 8. transmit interrupt ii ? desid descriptor id this bit field is a copy of the descriptor id of the transmit descriptor which is currently in use. it can be used for tracking purposes. thi (transmit) host initiated interrupt the ?(transmit) host initiated? interrupt vector is generated, if bit thi is set in a transmit descriptor and processing of this descriptor has finished. after receiving this interrupt vector, system software can release the descriptor, e.g. put the descriptor into a free pool. tab transmit abort the ?transmit abort? interrupt vector is generated, either when the ?transmit abort/branch? command was given and therefore one frame could not be transmitted completely or when no and fe were set to 0 in a transmit descriptor and previous frame was incompletely specified. 31 30 29 28 27 26 24 21 16 1 01 b 11 b queue(2:0) 0 0 desid(5:0) 15 14 12 7 0 thi tab 0 htab 0 0 0 0 chan(7:0) peb 20256 e pef 20256 e functional description data sheet 91 04.2001 htab hold caused transmit abort the ?hold caused transmit abort? interrupt vector is generated, when data management unit retrieved a transmit descriptor where hold was set and fe equals 0. the interrupt will be generated after the data section was transferred completely. after transmission of frame based protocols (hdlc, ppp) protocol machine appends abort sequence due to incomplete packet. chan channel number this bit field identifies the channel for which the information in the interrupt vector is valid. peb 20256 e pef 20256 e functional description data sheet 92 04.2001 4.7.1.5 command interrupts command interrupts are written to the command interrupt queue (interrupt queue eight). transmit interrupts ? tcf transmit command failed the ?transmit command failed? interrupt vector is issued, if the command ?transmit init? given via register cspec_cmd.xcmd could not be finished. this happens, when ? system software tried to allocate more buffer locations for a channel than were available. ? system software specified thresholds (transmit forward threshold, transmit refill threshold), which were greater than the specified transmit buffer size. note: the sum of both thresholds must be smaller than the transmit buffer size of a particular channel. erroneous programming does not result in the ?transmit command failed? interrupt vector. tcc transmit command complete the ?transmit command complete? interrupt vector is issued after successful completion of commands ?transmit init? and ?transmit off?, which can be issued via register cspec_cmd.xcmd . chan channel number this bit field contains the channel number of the affected channel. 31 30 27 17 16 1 0010 b 0 0 0 0 0 0 0 0 0 tcf tcc 15 7 0 0 0 0 0 0 0 0 0 chan(7:0) peb 20256 e pef 20256 e functional description data sheet 93 04.2001 receive interrupts ? rcc receive command complete the ?receive command complete? interrupt vector is issued after successful completion of commands ?receive init? and ?receive off?, which can be issued via register cspec_cmd.rcmd . chan channel number this bit field contains the channel number of the affected channel. 31 30 27 16 1 0000 b 0 0 0 0 0 0 0 0 0 0 rcc 15 7 0 0 0 0 0 0 0 0 0 chan(7:0) peb 20256 e pef 20256 e functional description data sheet 94 04.2001 4.7.2 mailbox interrupts to the local bus mailbox interrupts are stored in an internal interrupt fifo which is located inside the munich256 and can be read from either the local microprocessor or (for test purposes) via the chip internal bridge from the host processor located on the pci bus. the interrupt fifo triggers the lint pin which indicates that there is at least one interrupt vector available. then the interrupt fifo can be read from either pci side or local bus side. the interrupt vector contains a last indication when there is no further interrupt vector stored in the internal interrupt fifo. ? figure 4-15 mailbox interrupt notification interrupt fifo ebu interrupt control: intctrl interrupt status: intfifo iv local up interface interrupt bus ii mailbox int. vector setup: fconf.mid munich256 1 lint 2 3 1 . mailbox forwards interrupt vector to interrupt fifo. 2. interrupt controller asserts lint (if enabled). 3. microprocessor reads interrupt fifo. microprocessor peb 20256 e pef 20256 e functional description data sheet 95 04.2001 ? ? the ?mailbox? interrupt vector is generated, in case that the host cpu on pci side has written data to the mailbox status register mbp2e0. last last indication last indicates that at least one more valid interrupt vector is stored in the internal interrupt fifo. this bit is generated at read access time. 0 there is at least one more interrupt in the internal interrupt fifo. 1 this interrupt is the last interrupt that is stored in the internal interrupt fifo. status mailbox information the bit field status contains a copy of mbe2p0.mb(6:0). 15 14 13 7 6 5 4 0 last 0 status(6:0) 11 b 00000 b peb 20256 e pef 20256 e interface description data sheet 96 04.2001 5 interface description 5.1 pci interface a 32-bit and 66 mhz capable pci bus controller provides the interface between the munich256 and the host system. pci interface pins are measured as compliant to the 3.3v signalling environment according to the pci specification rev. 2.1. the pci bus controller operates as initiator or target. commands are supported as follows: ? master memory read single dword/burst of up to 64 dwords with zero wait cycles. ? master memory write single dword/burst of up to 64 dwords with zero wait cycles. ? slave memory read single dword. ? slave memory write single dword. fast back-to-back transfers are provided for slave accesses only. all read/write accesses to the munich256 must be 32-bit wide, that is all bytes must be enabled. non 32-bit accesses result in system interrupt. refer also to the pci specification rev. 2.1 for detailed information about pci bus protocol. 5.1.1 pci read transaction the transaction starts with an address phase which occurs during the first cycle when frame is activated (clock 1 in figure 5-1 ). during this phase the bus master (initiator) outputs a valid address on ad(31:0) and a valid bus command on c/ be (3:0). the first clock of the first data phase is clock 3. during the data phase c/ be indicate which byte lanes on ad(31: 0) are involved in the current data phase. the first data phase on a read transaction requires a turnaround cycle. in figure 5-1 the address is valid on clock 2 and then the master stops driving ad. the target drives the ad lines following the turnaround when devsel is asserted. ( trdy cannot be driven until devsel is asserted.) the earliest the target can provide valid data is clock 4. once enabled, the ad output buffers of the target stay enabled through the end of the transaction. a data phase may consist of a data transfer and wait cycles. a data phase completes when data is transferred, which occurs when both irdy and trdy are asserted. when either is deasserted a wait cycle is inserted. in the example below, data is successfully transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. the first data phase completes in the minimum time for a read transaction. the second data phase is extended on clock 5 because trdy is deasserted. the last data phase is extended because irdy is deasserted on clock 7. the master knows at clock 7 that the next data phase is the last. however, the master is not ready to complete the last peb 20256 e pef 20256 e interface description data sheet 97 04.2001 transfer, so irdy is deasserted on clock 7, and frame stays asserted. only when irdy is asserted can frame be deasserted, which occurs on clock 8. ? figure 5-1 pci read transaction 5.1.2 pci write transaction the transaction starts when frame is activated (clock 1 in figure 5-2 ). a write transaction is similar to a read transaction except no turnaround cycle is required following the address phase. in the example, the first and second data phases complete with zero wait cycles. the third data phase has three wait cycles inserted by the target. both initiator and target insert a wait cycle on clock 5. in the case where the initiator inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are withdrawn. the last data phase is characterized by irdy being asserted while the frame signal is deasserted. this data phase is completed when trdy goes active (clock 8). address data 1 data 2 data 3 command be's 1 2 3 4 5 6 7 8 clk frame ad c/be irdy trdy devsel wait wait wait data transfer data transfer data transfer address phase data phase data phase data phase bus transaction peb 20256 e pef 20256 e interface description data sheet 98 04.2001 ? figure 5-2 pci write transaction 5.2 spi interface (rom load unit) additional pins, which are not covered from the pci specification, but are closely related, are the spi pins. via the spi pins the vendor id and the vendor subsystem id can be loaded into the corresponding pci configuration registers during start-up of the device. the spi interface supports eeproms with an eight bit address space. after a system reset, the munich256 starts reading the first byte out of the connected eeprom at address 00 h . if this byte is equal aa h , the device continues reading out the memory contents. everytime four bytes are read out of the eeprom (starting with byte address 01 h ), the eeprom interface writes the read information to the pci configuration space. the first four bytes will be written to the pci configuration space address 00 h , the next four bytes to the pci configuration space address 04 h and so on. so the contents of the eeprom, starting with eeprom byte address 01 h , will be mapped over the pci configuration space after a system reset. during this configuration phase, all accesses to the pci interface will be answered with ?retry? by the pci interface. if the first byte in the eeprom is not equal aa h , the eeprom interface stops loading the pci configuration space immediately, and the pci interface can be accessed. the pci configuration space in this case contains the default values. the configuration mechanism through the serial interface can be disabled by pin spload. if this pin is connected to ?0?, the configuration mechanism is disabled. the address data 1 data 2 data 3 command 1 2 3 4 5 6 7 8 clk frame ad c/be irdy trdy devsel wait wait data transfer data transfer address phase data phase data phase data phase bus transaction be 1 be 2 be 3 wait wait peb 20256 e pef 20256 e interface description data sheet 99 04.2001 bridge can be accessed through the pci interface directly after a system reset. in this case the pci configuration space contains the default values. 5.2.1 accesses to a spi eeprom the eeprom contents can also be controlled (read and write) by the software. for this, a special eeprom control register is implemented as part of the pci configuration space. to start a read/write transaction to an connected eeprom, you have to set the command, the byte address (for read-/write data commands), the data to be written and the start indication by writing to the eeprom control register spi in the pci configuration space. if the interface detects spi.start asserted (= ?1?), it interprets the command and starts the read-/write transaction to the connected eeprom. after the transaction has finished, the eeprom control module deasserts the start bit. if the command was a read command (read status register, read data from memory array), the byte that was read out of the eeprom is available in the data register. for transactions started with the eeprom control register, the interface does not check if an eeprom is connected to the spi bus, because the eeprom is full passive. a full functional description of the spi commands and their usage as well as a description of the eeproms status register can be found in the description of the eeprom that will be selected by a board vendor. byte address for read and write transaction to the connected eeprom, the byte address must be written in this register before the transaction is started. data for the write status register transaction and the write data to memory array transactions, the data that has to be written to the eeprom must be written to this register before the transaction is started. after a read status register transaction or a read data from memory array transaction has finished (bit spi.start is deasserted), the byte received from the eeprom is available in this register. start to start the eeprom transaction defined via register spi the bit spi.start must be set to ?1? by a write transaction through the pci interface. after the transaction is finished, the eeprom start bit is deasserted by the eeprom interface controller. this signal has to be polled by system software. 5.2.2 spi read sequence the munich256 selects an external eeprom by pulling spcs low. the eight bit read sequence is transmitted followed by the eight bit address. after the read instruction and peb 20256 e pef 20256 e interface description data sheet 100 04.2001 address is sent, the data stored in the memory at the selected address is shifted in on the spsi pin. the read operation is terminated by setting spcs high (see figure 5-3 ). ? figure 5-3 spi read sequence 5.2.3 spi write sequence prior to any attempt to write data to an external eeprom, the write enable latch must be set by issuing the wren instruction. this is done by setting spcs low and then clocking out the wren instruction. after all eight bits of the instruction are transmitted, the spcs will be brought high to set the write enable latch. once the write enable latch is set, the user may proceed by issuing a write instruction, followed by the eight bit address and then the data to be written. in order that data will actually be written to the eeprom, the spcs is set high after the least significant bit (d0) of the data byte has been clocked in. refer to figure 5-4 for detailed illustrations on the byte write sequence. while the write is in progress, the register bit spi.start may be read to check the status of the transaction. when a write cycle is completed, the register bit spi.start is reset. ? figure 5-4 spi write sequence 0 1 2 3 4 5 6 7 8 9 14 15 16 17 18 19 20 21 22 23 7 6 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 instruction 8 bit address data in spcs spclk spso spsi 0 1 2 3 4 5 6 7 8 9 14 15 16 17 18 19 20 21 22 23 7 6 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 instruction 8 bit address data out spcs spclk spso spsi peb 20256 e pef 20256 e interface description data sheet 101 04.2001 5.3 local microprocessor interface the local microprocessor interface is a demultiplexed switchable intel or motorola style interface with master and slave functionality. the munich256 provides a local clock output lclk, which is a feed through of the pci system clock as clock reference for the local microprocessor interface. the local bus master capability allows to access peripherals located on the local bus via the pci interface. bit fconf.lme enables the bus master capability. the base address register two is disabled per default and can be enabled during start- up of the internal pci interface. this is done by setting bit mem.bar2 in the pci configuration space. the munich256 supports a maximum of three 8 kbyte pages of memory on the local address bus. the correspondence between the accessed pci memory space (mapped via base address register 2) and the asserted chip selects is shown in table 5-1. the mapping of the pci byte enables to the local bus address is dependent on the selected bus mode and is explained in detail in the corresponding section. table 5-1 correspondence between pci memory space and chip select page ad(14:0) lcs2 lcs1 0 0000 h - 1fff h 1 0 1 2000 h - 3fff h 0 1 2 4000 h - 5fff h 0 0 3 6000 h - 7fff h not valid peb 20256 e pef 20256 e interface description data sheet 102 04.2001 5.3.1 intel mode 5.3.1.1 slave mode in intel slave mode the bus interface supports 16-bit transactions in demultiplexed bus operation. it uses the local bus port pins la(12:1) for the 16 bit address and the local bus port pins ld(15:0) for 16 bit data. a read/write access is initiated by placing an address on the address bus and asserting lcs0 ( figure 5-5 ). the external processor then activates the respective command signal ( lrd , lwr ). data is driven onto the data bus either by the munich256 (for read cycles) or by the external processor (for write cycles). after a period of time, which is determined by the access time to the internal registers valid data is placed on the bus, which is indicated by asserting the active low signal lrdy . note: lcs0 need not be deasserted between two subsequent cycles to the same device. read cycles input data can be latched and the command signal can be deactivated now. this causes the munich256 to remove its data from the data bus which is then tri-stated again. lrdy is driven high and will be tri-stated as soon as lcs0 is deasserted. write cycles the command signal can be deactivated now. if a subsequent bus cycle is required, the external processor can place the respective address on the address bus. 5.3.1.2 master mode a read/write access from the pci bus to the 16 bit demultiplexed local bus is initiated by accessing the pci memory space base which is controlled by the base address register2. each valid read or write access to this base address triggers the local bus master interface which in turn starts arbitration for the local bus by asserting lhold (see (1) in figure5-6 ). as soon as the munich256 gets access to the local bus (lhlda asserted) it starts the local bus latency timer and begins a read/write transaction as the bus master. the signal lhold remains asserted while a transaction is in progress or as long as the local bus latency timer is not expired. a read/write transaction begins when the munich256 places a valid address on the address bus, sets the lbhe signal which indicates a 8- or 16-bit bus access and asserts the chip select signals lcs1 and/or lcs2 . then the munich256 activates the respective command signals ( lrd , lwr ). data is driven onto the data bus either by the munich256 (for write cycles) or by the accessed device (for read cycles). a transaction is finished on the local bus when the external device asserts lrdy (ready controlled bus cycles) or when the internal wait state timer expires. peb 20256 e pef 20256 e interface description data sheet 103 04.2001 ? figure 5-5 intel bus mode ? figure 5-6 intel bus arbitration valid c/ be combinations and the correspondence between local address, lbhe and the mapping of pci data to the local data bus are shown in table 5-2 and table 5-3. all address address data data read cycle (16 bit) write cycle (8 bit 1 ) la(12:0) lcs0 (in) lcs1,2 (out) lrd lwr lrdy 2 ld(15:0) lbhe 1 note 1: supported in local bus master mode only. note 2: ready controlled bus cycles only. lhold lhlda bus cycle 1 2 one or more read/write cycles as bus master 3 lhold remains asserted as long as a transaction is in progress or while the latency timer is not expired read/write cycle peb 20256 e pef 20256 e interface description data sheet 104 04.2001 accesses not shown in the table result in generation of a ?pci access error? interrupt vector. table 5-2 c/ be to la/ lbhe mapping in intel bus mode (8 bit port mode) table 5-3 c/ be to la/ lbhe mapping in intel bus mode (16 bit port mode) c/ be (3:0) la(1:0) lbhe ld(15:8) ld(7:0) 1110 b 00 b 1 - ad(7:0) 1101 b 01 b 1 - ad(15:8) 1011 b 10 b 1 - ad(23:16) 0111 b 11 b 1 - ad(31:24) c/ be (3:0) la(1:0) lbhe ld(15:8) ld(7:0) 1110 b 00 b 1 - ad(7:0) 1101 b 01 b 0 ad(15:8) - 1011 b 10 b 1 - ad(23:16) 0111 b 11 b 0 ad(31:24) - 1100 b 00 b 0 ad(15:8) ad(7:0) 0011 b 10 b 0 ad(31:24) ad(23:16) peb 20256 e pef 20256 e interface description data sheet 105 04.2001 5.3.2 motorola mode 5.3.2.1 slave mode the demultiplexed bus modes use the local bus port pins la(12:1) for the 16- bit address and the local bus port pins ld(15:0) for 16 bit data. a read/write access is initiated by placing an address on the address bus and asserting lcs0 together with the command signal lwr rd (see ? motorola bus mode ? on page106 ). the data cycle begins when the signal lds is asserted. data is driven onto the data bus either by the munich256 (for read cycles) or by the external processor (for write cycles). after a period of time, which is determined by the access time to the internal registers valid data is placed on the bus, which is indicated by asserting the active low signal ldtack . note: lcs0 need not be deasserted between two subsequent cycles to the same device. read cycles input data can be latched and the data strobe signal can be deactivated now. this causes the munich256 to remove its data from the data bus which is then tri-stated again. ldtack is driven high and will be tri-stated as soon as lcs0 is deasserted. write cycles the data strobe signal can be deactivated now. if a subsequent bus cycle is required, the external processor can place the respective address on the address bus. 5.3.2.2 master mode as in intel mode a read/write access from the pci bus to the 16 bit demultiplexed local bus is initiated by accessing the pci memory space base mapped by the base address register 2. each valid read or write access to this base address triggers the local bus master interface which in turn starts arbitration for the local bus using the interface signals lbr and lbg and lbgack . as soon as the munich256 gets access to the local bus it places a valid address on the address bus, sets the lsize0 signal which indicates a 8- or 16-bit bus access and asserts the corresponding chip select signal. the signal lwr rd indicates a read or write operation. the data cycle begins when the signal lds is asserted. data is driven onto the data bus either by the munich256 or by the external component. a transaction is finished on the local bus when the external device asserts the active low signal ldtack or when the internal wait state timer expires. peb 20256 e pef 20256 e interface description data sheet 106 04.2001 ? figure 5-7 motorola bus mode ? figure 5-8 motorola bus arbitration address address data data read cycle (8 bit 1 ) write cycle (16 bit) la(12:0) lds lrdwr ldtack 2 ld(15:0) lsize0 1 lcs0 (in) lcs1,2 (out) note 1: supported in local bus master mode only. note 2: ldtack controlled bus cycles only. lbr lbg bus cycle 1 2 one or more read/write cycles as bus master 3 lbgack remains asserted as long as a transaction is in progress or while the latency timer is not expired. lbgack rd/wr cycle peb 20256 e pef 20256 e interface description data sheet 107 04.2001 the address and byte enable signals on the pci bus are mapped to the local bus according to table 5-4 and table 5-5. it can be seen that the munich256 supports different valid c/ be combinations which result in either a 8- or 16-bit access to the local bus interface. all accesses not shown in the table result in generation of a ?pci access error? interrupt vector. byte swapping for 16 bit data transfers can be disabled. table 5-4 c/ be to la/lsize0 mapping in motorola bus mode (8 bit port mode) table 5-5 c/ be to la/lsize0 mapping in motorola bus mode (16 bit port mode) 5.4 serial line interface the serial interface of the interface can be configured in a 16-port mode and additionally in a 28-port mode. dependent on the port configuration (16-port mode or 28-port mode) the munich256 supports t1, e1, channelized 4.096 mhz, channelized 8.192 mhz or unchannelized frame structures ( figure 5-9 ). c/ be (3:0) la(1:0) lsize0 ld(15:8) ld(7:0) 1110 b 00 b 1 ad(7:0) - 1101 b 01 b 1 ad(15:8) - 1011 b 10 b 1 ad(23:16) - 0111 b 11 b 1 ad(31:24) - c/ be (3:0) la(1:0) lsize0 ld(15:8) ld(7:0) 1110 b 00 b 1 ad(7:0) 1101 b 01 b 1 - ad(15:8) 1011 b 10 b 1 ad(23:16) - 0111 b 11 b 1 - ad(31:24) 1100 b 00 b 0 ad(7:0) ad(15:8) 0011 b 10 b 0 ad(23:16) ad(31:24) peb 20256 e pef 20256 e interface description data sheet 108 04.2001 ? figure 5-9 supported frame structures 5.4.1 interface timing in 16-port mode in 16-port mode each receive port has a receive data input rd(x), a receive synchronization input rsp(x) and the corresponding receive clock input rclk(x). in transmit direction each port consists of the transmit data output td(x), the transmit 0 f 1 2 21 22 23 0 f 1 2 f 1 2 3 4 5 6 7 0 0 frame timeslot 0 0 1 2 29 30 31 0 1 2 1 2 3 4 5 6 7 0 0 frame 1 timeslot 0 2 3 4 29 30 31 28 4 5 6 7 7 3 2 1 6 5 22 23 23 4 22 a) t1 frame structure b) e1 frame structure b0 b1 b3 b4 b5 b6 b0 b2 b7 b7 b1 b6 b2 e) unchannelized mode octet 1 2 3 4 5 6 7 0 0 1 2 4 5 6 7 3 0 1 2 61 62 63 0 1 2 1 2 3 4 5 6 7 0 0 frame 1 timeslot 0 2 3 4 61 62 63 60 4 5 6 7 c) 4.092 mhz frame structure ( 16-port mode only ) 0 1 2 125 126 127 0 1 2 1 2 3 4 5 6 7 0 0 frame 1 timeslot 0 2 3 4 125 126 127 124 4 5 6 7 d) 8.192 mhz frame structure ( 16-port mode only ) peb 20256 e pef 20256 e interface description data sheet 109 04.2001 synchronization input tsp(x) and the transmit clock input tclk(x). in channelized mode (t1, e1, 4.096 mhz and 8.192 mhz) the high level after a low to high transition of the frame synchronization pulse marks the last bit of a frame (default value in transmit direction) respectively the first bit of a frame (default value in receive direction). the active edge of the frame synchronization pulse can be shifted in a range of -4 to +3. rd(x), rsp(x) and tsp(x) can be sampled on the rising or falling edge of the receive clock respectively the transmit clock. outgoing data is updated on the rising or falling edge of tclk(x). ? figure 5-10 t1 mode frame timing b0 b1 b3 b4 b5 b6 td(x) 1 tsp(x) 1 1. tsp(x) sampled with the rising edge of tclk(x), td(x) updated with the falling edge of tclk(x). 2. in given example transmit bit shift is set to zero. b0 b2 b7 b7 b4 b5 b6 3 2 1 0 -1 -2 -3 transmit bit shift 2 tclk(x) 1 f 1 2 3 4 5 6 7 0 0 7 1 6 5 4 timeslot 0 -4 b3 3 t1 frame b0 b1 b3 b4 b5 b6 rd(x) 3 rsp(x) 3 3. rsp(x) sampled with the rising edge of rclk(x), rd(x) sampled with the rising edge of rclk(x). 4. in given example receive bit shift is set to one. b0 b2 b7 b7 b4 b5 b6 3 2 1 0 -1 -2 -3 receive bit shift 4 rclk(x) 3 f 1 2 3 4 5 6 7 0 0 7 1 6 5 4 timeslot 0 -4 b3 3 t1 frame b1 peb 20256 e pef 20256 e interface description data sheet 110 04.2001 ? figure 5-11 e1, 4.096 mhz and 8.192 mhz interface timing in 16-port mode b0 b1 b3 b4 b5 b6 td(x) 1 tsp(x) 1 1. tsp(x) sampled with the rising edge of tclk(x), td(x) updated with the falling edge of tclk(x). 2. in given example transmit bit shift is set to zero. b0 b2 b7 b7 b4 b5 b6 3 2 1 0 -1 -2 -3 transmit bit shift 2 tclk(x) 1 -4 b3 e1 frame, 4.096 mhz frame or 8.192 mhz frame b0 b1 b3 b4 b5 b6 rd(x) 3 rsp(x) 3 3. rsp(x) sampled with the rising edge of rclk(x), rd(x) sampled with the rising edge of rclk(x). 4. in given example receive bit shift is set to one. b0 b2 b7 b7 b4 b5 b6 3 2 1 0 -1 -2 -3 receive bit shift 4 rclk(x) 3 -4 b3 b1 1 2 3 4 5 6 7 0 0 1 timeslot 0 4 5 6 7 3 2 1 2 3 4 5 6 7 0 0 1 timeslot 0 4 5 6 7 3 2 b2 b1 time slot 31 (e1), 63 (4.096 mhz), 127 (8.192 mhz) e1 frame, 4.096 mhz frame or 8.192 mhz frame time slot 31 (e1), 63 (4.096 mhz), 127 (8.192 mhz) peb 20256 e pef 20256 e interface description data sheet 111 04.2001 ? figure 5-12 unchannelized mode interface timing 5.4.2 interface timing in 28-port mode the munich256 in 28-port mode supports t1, e1 and unchannelized frame structures on the serial side. each receive port has a receive data input rd(x) and the corresponding receive clock input rclk(x). in transmit direction each port consists of the transmit data output td(x) and the transmit clock input tclk(x). in t1 and e1 mode a clock gap marks the beginning of a frame. the timing of the unchannelized mode is identical to the 16-port mode. ? figure 5-13 t1-mode interface timing in 28-port mode b0 b1 b3 b4 b5 b6 1 2 3 4 5 6 7 0 0 octet tclk(x) td(x) 2 rclk(x) rd(x) 3 b0 b2 b7 b7 b1 b0 b1 b3 b4 b5 b6 b0 b2 b7 b7 b1 1 1. reference clock is provided for high speed port #0. 2. td(x) can be transmitted synchronous to the rising or the falling edge of tclk(x). 3. rd(x) can be sampled on the rising or falling edge of rclk(x). reference clock 1 0 1 2 3 b6 b2 b3 b2 b6 b0 b1 b3 b4 b5 b6 td(x) 1 1. td(x) updated with the falling edge of tclk(x). b0 b2 b7 b7 b4 b5 b6 tclk(x) 1 f 1 2 3 4 5 6 7 0 0 7 1 6 5 4 timeslot 0 b3 3 t1 frame b0 b1 b3 b4 b5 b6 rd(x) 2 2. rd(x) sampled with the rising edge of rclk(x). b0 b2 b7 b7 b4 b5 b6 rclk(x) 2 f 1 2 3 4 5 6 7 0 0 7 1 6 5 4 timeslot 0 b3 3 t1 frame b1 peb 20256 e pef 20256 e interface description data sheet 112 04.2001 ? figure 5-14 e1-mode interface timing in 28-port mode 5.5 jtag interface a test access port (tap) is implemented in the munich256. the essential part of the tap is a finite state machine (16 states) controlling the different operational modes of the boundary scan. both, tap controller and boundary scan, meet the requirements given by the jtag standard: ieee 1149.1. figure 5-15 gives an overview about the tap controller. b0 b1 b3 b4 b5 b6 td(x) 1 1. td(x) updated with the falling edge of tclk(x). b0 b2 b7 b7 b4 b5 b6 tclk(x) 1 b3 e1 frame b0 b1 b3 b4 b5 b6 rd(x) 2 2. rd(x) sampled with the rising edge of rclk(x). b0 b2 b7 b7 b4 b5 b6 rclk(x) 2 b3 e1 frame b1 1 2 3 4 5 6 7 0 0 1 timeslot 0 4 5 6 7 3 2 1 2 3 4 5 6 7 0 0 1 timeslot 0 4 5 6 7 3 2 b2 b1 peb 20256 e pef 20256 e interface description data sheet 113 04.2001 ? figure 5-15 block diagram of test access port and boundary scan unit if no boundary scan operation is planned trst has to be connected with v ss . tms and tdi do not need to be connected since pull- up transistors ensure high input levels in this case. nevertheless it would be a good practice to put the unused inputs to defined levels. in this case, if the jtag is not used: tms = tck = ?1? is recommended. test handling (boundary scan operation) is performed via the pins tck (test clock), tms (test mode select), tdi (test data input) and tdo (test data output) when the tap controller is not in its reset state, i. e. trst is connected to v dd3 or it remains unconnected due to its internal pull up. test data at tdi are loaded with a clock signal connected to tck. ?1? or ?0? on tms causes a transition from one controller state to another; constant ?1? on tms leads to normal operation of the chip. an input pin (i) uses one boundary scan cell (data in), an output pin (o) uses two cells (data out, enable) and an i/o-pin (i/o) uses three cells (data in, data out, enable). note that most functional output and input pins of the munich256 are tested as i/o pins in boundary scan, hence using three cells. the boundary scan unit of the munich256 contains a total of n = 484 scan cells. the desired test mode is selected by serially loading a 4-bit instruction code into the instruction register via tdi (lsb first). extest is used to examine the interconnection of the devices on the board. in this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values (?0? or ?1?). then the contents of the boundary scan is shifted to tdo. at the same time the next scan vector is loaded from tdi. subsequently all output pins are updated according to the new clock generation test access port (tap) tap controller - finite state machine - instruction register (4 bit) - test signal generator clock tck trst tms reset data in tdi test control tdo enable data out clock identification scan (32 bit) boundary scan (n bit) control bus id data out ss data out n . . . . . . 1 2 pins peb 20256 e pef 20256 e interface description data sheet 114 04.2001 boundary scan contents and all input pins again capture the current external level afterwards, and so on. intest supports internal testing of the chip, i. e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (?0? or ?1?). the resulting boundary scan vector is shifted to tdo. the next test vector is serially loaded via tdi. then all input pins are updated for the following test cycle. sample/preload is a test mode which provides a snapshot of pin levels during normal operation. idcode : a 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to ?1?. the id code field is set to version : 2 h part number : 005b h manufacturer : 083 h (including lsb, which is fixed to ?1?) note: since in test logic reset state the code ?0011? is automatically loaded into the instruction register, the id code can easily be read out in shift dr state. bypass : a bit entering tdi is shifted to tdo after one tck clock cycle. clamp allows the state of signals driven from component pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between tdi and tdo. signals driven from the munich256 will not change while the clamp instruction is selected. highz places all of the system outputs in an inactive drive state. peb 20256 e pef 20256 e channel programming / reprogramming concept data sheet 115 04.2001 6 channel programming / reprogramming concept for channel programming the munich256 provides a on-chip channel specification data structure. all information necessary to setup a channel has to be provided using this data structure. as soon as all channel information has been written to the channel specification registers the information can be released using simple channel commands, which have to be written to register cspec_cmd. the relevant channel information will then be copied to the chip internal channel database. the channel specification registers, which need to be programmed before a command can be executed, are shown in table 6-1 . before initializing a channel the time slot assignment process for the affected channel must be completed. vice versa after shutting down a channel the time slots associated with the affected channel should be set to inhibit. otherwise if a time slot is reprogrammed afterwards, strange behavior can be expected on the serial side. for each channel a simple sequence of channel commands must be ensured. after reset each channel is in its ?off? state. therefore, the first command to start a channel is ?transmit init? or ?receive init?. this brings the channel into the operational state. in this state all commands except ?transmit init?, ?receive init? or ?transmit idle can be given. to bring a channel back into the idle state a ?transmit off? or ?receive off? command has to be programmed. for certain channel commands system software has to wait before new commands can be given for the same channel. this is due to internal buffer allocation functions which require some processing time. notification of system software is done in form of command interrupt vectors, which signal that a command has successful or even unsuccessful completed. table 6-1 channel specification registers and channel commands register transmit commands receive commands t r a n s m i t i n i t t r a n s m i t o f f t r a n s m i t a b o r t / b r a n c h t r a n s m i t h o l d r e s e t t r a n s m i t i d l e t r a n s m i t d e b u g t r a n s m i t u p d a t e f n u m r e c e i v e i n i t r e c e i v e o f f r e c e i v e a b o r t / b r a n c h r e c e i v e h o l d r e s e t r e c e i v e d e b u g cspec_mode_rec cspec_rec_accm cspec_mode_xmit peb 20256 e pef 20256 e channel programming / reprogramming concept data sheet 116 04.2001 6.1 channel commands the following section describes all receive and transmit channel commands and the programming sequence in details. 6.2 transmit channel commands transmit init before a ?transmit init? command is given, the munich256 will not transmit data for a channel. after the ?transmit init? command the channel database of the affected channel is initialized according to the parameters in the channel specification registers. after initialization the transmit buffer prepares the buffer locations for the selected channel and the data management unit starts processing the linked list and fills the prepared buffer locations. in order to prevent a transmit underrun condition, the transmit buffer is filled up to the transmit forward threshold before data is sent to the serial side. the protocol machine formats data according to the given channel parameters and the data is placed in the time slots assigned to the selected channel. when no or not sufficient data is available, the device sends the idle code according the selected protocol mode. if the command was successful, a ?transmit command complete? interrupt vector is generated after the first transmit descriptor is read pointed to by register cspec_ftda. in case that there is insufficient transmit buffer space, the command cannot be cspec_xmit_accm cspec_buffer cspec_frda cspec_ftda cspec_imask register transmit commands receive commands t r a n s m i t i n i t t r a n s m i t o f f t r a n s m i t a b o r t / b r a n c h t r a n s m i t h o l d r e s e t t r a n s m i t i d l e t r a n s m i t d e b u g t r a n s m i t u p d a t e f n u m r e c e i v e i n i t r e c e i v e o f f r e c e i v e a b o r t / b r a n c h r e c e i v e h o l d r e s e t r e c e i v e d e b u g peb 20256 e pef 20256 e channel programming / reprogramming concept data sheet 117 04.2001 completed internally and the device responds with a ?transmit command failed? interrupt vector. furthermore the munich256 will not start processing the linked list for this particular channel. new commands for the same channel may be given after the user received the ?transmit command complete? interrupt vector. prior to new initialization of the same channel it must be turned off using the ?transmit off? command. transmit off after ?transmit off? the transmit channel is disabled immediately and the time slots assigned to the selected channel are tri-stated . the transmit buffer releases all buffer locations assigned to the channel. the data management unit updates the last processed descriptor with the complete bit if enabled and generates a ?transmit host initiated? interrupt vector if the thi bit in the last descriptor was set. all channel related informations are cleared from the internal channel database. a ?transmit command complete? interrupt vector is generated when the channel command is finished. after that time processing of the linked list is completely stopped. new commands for the same channel may be given after the user received the ?transmit command complete? interrupt vector. transmit abort/branch the ?transmit abort/branch? command is performed on the serial side and in the data management unit. the data management unit stops immediately processing the current descriptor and branches to a new descriptor pointed to by cspec_ftda. data which is already stored in the transmit buffer is sent on the serial side. the protocol machine will append an abort sequence if data in transmit buffer was not complete due to ?transmit abort/branch? command. system software is informed about the aborted frame by a ?transmit abort? channel interrupt vector. if no data is stored in the transmit buffer this command does not affect the serial side and no ?transmit abort? interrupt vector is generated. data transmission is continued with a new frame when the data management unit branched to the new descriptor list. a ?transmit command complete? interrupt vector is generated after the management unit released the old descriptor list. new commands for the same channel may be given after the user received the ?transmit command complete? interrupt vector. transmit hold reset the ?transmit hold reset? command must be given after system software has set the hold bit of a descriptor from ?1? to ?0?. in case that the munich256 is in hold condition it reads the descriptor which had its hold bit set and tests the hold bit of the descriptor. if the hold bit is set to ?0? the data management unit branches to the next descriptor and continues data transmission. otherwise the particular channel remains in hold condition. peb 20256 e pef 20256 e channel programming / reprogramming concept data sheet 118 04.2001 the munich256 will not generate a ?transmit command complete? interrupt vector after this command is programmed. transmit update fnum the ?transmit update fnum? command changes the parameter cspec_mode_xmit.fnum in the internal channel database, which allows to change dynamically the number of idle flags that are inserted between two frames. the munich256 will not generate a ?transmit command complete? interrupt vector after this command is programmed. transmit idle the ?transmit idle? command starts the munich256 to send the value cspec_mode_xmit.tflag in the time slots of the selected channel. this command can only be given if a channel is turned off. the munich256 will not generate a ?transmit command complete? interrupt vector after this command is programmed. transmit debug the ?transmit debug? command allows to read back the current settings of the internal channel database. after the ?transmit debug? command has been programmed system software can read back the current values of the channel specification registers. register cspec_ftda contains the value of the next transmit descriptor. the munich256 will not generate a ?transmit command complete? interrupt vector after this command is programmed. note: the setting of the internal channel database is not copied into the channel specification registers and therefore the values read can not be used to program another channel. after system software has used the ?transmit debug? command it must reprogram the channel specification registers to setup a new channel. 6.3 receive channel commands receive init before a ?receive init? command is given, the munich256 will not process data for a channel. after the ?receive init? command the channel database of the affected channel is initialized according to the parameters programmed in channel specification registers. after initialization data received in those time slots assigned to the selected channel is processed and stored in the internal receive buffer. the data management unit starts storing this data in the linked list which starts at cspec_frda. the protocol machine deformats and checks data according to the given channel parameters. peb 20256 e pef 20256 e channel programming / reprogramming concept data sheet 119 04.2001 a ?receive command complete? interrupt vector is generated after the channel information is copied into the internal channel database. new commands for the same channel may be given after the munich256 issued the ?receive command complete? interrupt vector. prior to new initialization of the same channel it must be turned off using the ?receive off? command. receive off the ?receive off? command disables the receive channel immediately. further incoming data is discarded until the next ?receive init? command is given. data already stored in the receive buffer is written to system memory. if a frame is destroyed by the ?receive off? command a ?receive abort? channel interrupt vector is generated. a ?receive command complete? interrupt vector is generated after remaining data in the receive buffer is written to system memory. after that time processing of the linked list is stopped and the channel information is cleared from the internal channel database. new commands for the same channel may be given after the munich256 issued the ?receive command complete? interrupt vector. receive abort/branch the ?receive abort/branch? command is performed in the data management unit. the data management unit stops immediately processing the current descriptor and branches to a new descriptor pointed to by cspec_frda. in case that the ?receive abort/branch? command is issued while a packet is written to system memory a ?receive abort? interrupt vector is generated and the rest of the frame already stored in receive buffer is discarded. data reception is continued with a new frame when the data management unit branched to the new descriptor list. a ?receive command complete? interrupt vector is generated after the channel information is copied into the internal channel database. new commands for the same channel may be given after the munich256 issued the ?receive command complete? interrupt vector. receive hold reset the ?receive hold reset? command must be given after system software has set the hold bit of a receive descriptor from ?1? to ?0?. in case that the munich256 is in hold condition it reads the descriptor which had its hold bit set and tests the hold bit of the descriptor. if the hold bit is set to ?0? the data management unit branches to the next descriptor and continues data reception. otherwise the particular channel remains in hold condition. the munich256 will not generate a ?receive command complete? interrupt vector after this command is programmed. peb 20256 e pef 20256 e channel programming / reprogramming concept data sheet 120 04.2001 receive debug the ?receive debug? command allows to read back the current settings of the internal channel database. after the ?receive debug? command has been programmed system software can read back the current values of the channel specification registers. register cspec_frda contains the value of the next receive descriptor. the munich256 will not generate a ?receive command complete? interrupt vector after this command is programmed. note: the setting of the internal channel database is not copied into the channel specification registers and therefore the values read can not be used to program another channel. after system software has used the ?receive debug? command it must reprogram the channel specification registers to setup a new channel. peb 20256 e pef 20256 e reset and initialization procedure data sheet 121 04.2001 7 reset and initialization procedure since the term ?initialization? can have different meanings, the following definition applies: chip initialization generating defined values in all on-chip registers, rams (if required), flip-flops etc. mode initialization software procedure, that prepares the device to its required operation, i.e. mainly writing on-chip registers to prepare the device for operation in the respective system environment. operational programming software procedures that setup, maintain and shut down operational modes, i.e. initialize logical channel or maintain framing operations on selected ports. 7.1 chip initialization hardware reset the hardware reset rst has to be applied to the device. chip input trst must be activated prior to or while asserting rst and should be held asserted as long as the boundary scan operation is not required. system clock must start running during reset. during reset: ? all i/os and all outputs are tri-state. ? all registers, state machines, flip-flops etc. are set asynchronously to their reset values and all internal modules are set to their initial state. ? all interrupts are masked. ? the register bit conf1.stop is set to ?1?. after hardware reset ( rst deasserted) system clock clk is assumed to be running. serial clocks must be low/high or running. the pci and the local bus interface pins go into their idle state. all serial line outputs are tri-state. the pci interface becomes active and depending on input pin spload starts to read subsystem id/subsystem vendor id and memory commands out of external eeprom via the spi interface. the serial clock is derived from the pci clock. as long as this procedure is active, the pci interface answers all accesses with retry. after the pci interface has finished its self initialization it can be configured with pci configuration cycles. in parallel to pci self initialization the internal modules start their ram initialization. as long as the ram initialization is running the internal modules indicate this condition with peb 20256 e pef 20256 e reset and initialization procedure data sheet 122 04.2001 their initialization in progress signal. the register bit conf1.iip is the result of all signals. as soon as all internal modules have finished their ram initialization the register bit conf1.iip is deasserted. software must poll the register bit conf1.iip until this bit has been deasserted. read access to registers other than conf1 is prohibited and may result in unexpected behavior of the design. write accesses are not allowed. chip initialization is finished when conf1.iip is ?0?. software reset alternately the munich256 provides the capability to issue a software reset via register bit conf1.srst. during software reset all interfaces except pci interface are forced into their idle state. after software reset is set the munich256 starts its self initialization and iip will be asserted. chip initialization is finished when conf1.iip is deasserted. afterwards the software reset bit must be set to ?0? to allow further operation. 7.2 mode initialization after chip initialization is finished the system software has to setup the device for the required function. the system software has to poll bit conf1.iip (fconf.iip). as soon as conf1.iip is deasserted, the system software has to clear bit conf1.stop and has to set the general operating modes in register conf1. the port mode has to be programmed. it is assumed, that port clocks are active according to the selected port mode. the ports shall be disabled, thus no incoming data is forwarded to the time slot assigner and the outputs are still tri-state. transmit direction the ports have to enabled via register ten. the transmit port synchronizes to the external synchronization pulse. after a port has been enabled payload data is provided from the time slot assigner. since the time slot assignment is in reset state, that is all time slots are set to inhibit, data bits are tri-state. receive direction the ports have to be enabled via register ren. the receiver synchronizes to the external synchronization pulse. as soon as frame synchronization has been achieved, incoming payload data is passed to the time slot assigner. since the time slot assignment is in the reset state, that is all time slots are set to inhibit, data bits are discarded. peb 20256 e pef 20256 e register description data sheet 123 04.2001 8 register description the register description of the munich256 is divided into two parts, an overview of all internal registers and in the second part a detailed description of all internal registers. 8.1 register overview the first part of the register overview describes the pci configuration space registers. the second part describes the register set which can be accessed from pci side only. these registers are used to setup the main operation modes and to run the channel engines of the device. the last part describes the register set of the mailbox and the local interrupt fifo. these registers may be accessed through the local microprocessor interface or via pci. note: register locations not contained in the following register tables are ?reserved?. in general all write accesses to reserved registers are discarded and read access to reserved registers result in 00000000 h . nevertheless, to allow future extensions, system software shall access documented registers only, since writes to reserved registers may result in unexpected behavior. the read value of reserved registers shall be handled as don?t care. unused and reserved bits are marked with a gray box. the same rules as given for register accesses apply to reserved bits, except that system software shall write the documented default value in reserved bit locations. 8.1.1 pci configuration register set (direct access) table 8-1 pci configuration register set register access address reset value comment page standard configuration space register did/vid r 00 h 2106110a h device id/vendor id 129 sta/cmd r/w 04 h 02a00000 h status/command 130 cc/rid r 08 h 02800001 h class code/revision id 132 bist/ head/ latim/ clsiz r/w 0c h 00000000 h built-in self test/ header type/ latency timer/ cache line size 133 bar1 r/w 10 h 00000000 h base address 1 134 bar2 r/w 14 h 00000000 h base address 2 135 barx r 14 h -24 h 00000000 h base address not used peb 20256 e pef 20256 e register description data sheet 124 04.2001 cisp r 28 h 00000000 h cardbus cis pointer ssid/ ssvid r 2c h 00000000 h subsystem id/ subsystem vendor id 136 erbad r 30 h 00000000 h expansion rom base adr. reserved r 34 h 00000000 h reserved reserved r 38 h 00000000 h reserved maxlat/ mingnt/ intpin/ intlin r/w 3c h 06020100 h maximum latency/ minimum grant/ interrupt pin/ interrupt line 137 user defined configuration space register spi r/w 40 h 0000001f h spi access register 138 req r/w 44 h 00000000 h req/gnt config register 140 mem r/w 48 h 000007e6 h pci memory command 141 debug r 4c h 00000000 h pci debug support 143 register access address reset value comment page peb 20256 e pef 20256 e register description data sheet 125 04.2001 8.1.2 pci slave register set (direct access) this section shows all registers which are located on the first configuration bus. these registers are used to setup the basic operating modes of the device and to setup the port, time slots and channels. system software has access to these registers via the pci bus. table 8-2 pci slave register set register access address reset value comment page general control conf1 r/w 040 h 820000f1 h configuration register 1 161 conf2 r/w 044 h 00000000 h configuration register 2 164 conf3 r/w 048 h 00090000 h configuration register 3 166 rbaft w 04c h 00000000 h receive buffer access failed interrupt threshold 167 sfdt w 050 h 00000000 h small frame dropped interrupt threshold register 168 interrupt control pci bus side iqia r/w 0e0 h 00000000 h interrupt queue initialization 186 iqba r/w 0e4 h 00000000 h interrupt queue base addr. 188 iqbl r/w 0e8 h 00000000 h interrupt queue length 189 iqmask r/w 0ec h 00000000 h interrupt queue mask 190 gista/giack r/w 0f0 h 00000000 h global interrupt status/ global interrupt acknowledge 191 gmask r/w 0f4 h ffffffff h interrupt mask 193 channel specification registers (* = cspec) *_cmd w 000 h 00000000 h command 144 *_mode_rec r/w 004 h 00000000 h mode receive 146 *_rec_accm r/w 008 h 00000000 h receiver accm map 149 *_mode_xmit r/w 014 h 00000000 h mode transmit 150 *_xmit_accm r/w 018 h 00000000 h transmit accm map 153 *_buffer r/w 020 h 00200000 h buffer configuration 154 *_frda r/w 024 h 00000000 h first receive descriptor addr. 157 peb 20256 e pef 20256 e register description data sheet 126 04.2001 *_ftda r/w 028 h 00000000 h first transmit descriptor address 158 *_imask r/w 02c h 00000000 h interrupt vector mask 159 port and time slot control registers pmiar r/w 060 h 00000000 h port mode indirect access 169 pmr r/w 064 h 0104c000 h port mode 170 ren r/w 068 h 00000000 h receive enable 173 ten r/w 06c h 00000000 h transmit enable 174 tsaia r/w 070 h 00000000 h time slot assignment indirect access 175 tsad r/w 074 h 02000000 h time slot assignment data 177 ppp character map/ demap registers rec_accmx r/w 080 h 00000000 h receive extended accm map 179 xmit_accmx r/w 090 h 00000000 transmit extended accm map 183 receive buffer control rbmon r 0b0 h 02000bff h receive buffer monitor 184 rbth r/w 0b4 h 02000001 h receive buffer threshold report 185 maintenance rbafc r 084 h 00000000 h receive buffer access failed counter 180 sfdia r/w 088 h 00000000 h small frame dropped indirect access 181 sfdc r 08c h 00000000 h small frame dropped counter 182 register access address reset value comment page peb 20256 e pef 20256 e register description data sheet 127 04.2001 8.1.3 pci and local bus register set (direct access) this section describes the registers which are located on the configuration bus ii (see also these registers can be accessed either from pci bus via the internal bus bridge or from the local bus side. note: since the local bus is 16-bit wide and the pci bus is 32-bit wide, the upper 16 bit of data coming from/to pci are discarded. note: please note that read accesses to local bus registers via pci bus and therefore the internal bus bridge may result in latencies which exceed the 16 clock rule of pci specification. exceeding the 16 clock rule results in target initiated retry on pci bus. in this case the read cycle needs to be repeated. table 8-3 pci and local bus slave register set register access address (pci) address (local bus) reset value comment page fconf r/w 100 h 00 h 8080 h configuration register 194 mtimer r/w 10 4 h 00 h 0001 h master local bus timer 196 interrupt control for local bus side intctrl r/w 108 h 04 h 0001 h interrupt control 197 intfifo r 10c h 06 h ffff h interrupt fifo 198 mailbox registers mbe2p0 r/w 140 h 20 h 0000 h mailbox local bus to pci command 199 mbe2p1 mbe2p2 mbe2p3 mbe2p4 mbe2p5 mbe2p6 mbe2p7 r/w 144 h 148 h 14c h 150 h 154 h 158 h 15c h 22 h 24 h 26 h 28 h 2a h 2c h 2e h 0000 h mailbox local bus to pci data registers 1 through 7 200 mbp2e0 r/w 160 h 30 h 0000 h mailbox pci to local bus command 201 peb 20256 e pef 20256 e register description data sheet 128 04.2001 mbp2e1 mbp2e2 mbp2e3 mbp2e4 mbp2e5 mbp2e6 mbp2e7 r/w 164 h 168 h 16c h 170 h 174 h 178 h 17c h 32 h 34 h 36 h 38 h 3a h 3c h 3e h 0000 h mailbox pci to local bus data registers 1 through 7 202 register access address (pci) address (local bus) reset value comment page peb 20256 e pef 20256 e register description data sheet 129 04.2001 8.2 detailed register description 8.2.1 pci configuration register did/vid device id/vendor id access : read address : 00 h reset value : 2106110a h did device id the device id identifies the particular device. it is hardwired to value 2106 h . vid vendor id the vendor id identifies the manufacturer of the device. it is hardwired to value 110a h . 31 16 did(15:0) 15 0 vid(15:0) peb 20256 e pef 20256 e register description data sheet 130 04.2001 stat/cmd status/command register access : read/write address : 04 h reset value : 02a00000 h dpe detected parity error this bit will be asserted whenever the munich256 detects a parity error. 0 no parity error detected. 1 parity error detected. this bit will be cleared by writing a ?1? to this bit position. sse signaled system error this bit will be asserted whenever the munich256 asserted serr . for system error conditions see bit se. 0 no system error signaled. 1 system error has been signaled. this bit will be cleared by writing a ?1? to this bit position. rma received master abort this bit will set whenever a transaction in which the munich256 acted as bus master was terminated with master abort. 0 no master abort detected. 1 transaction terminated with master abort. this bit will be cleared by writing a ?1? to this bit. 31 30 29 28 27 26 25 24 23 22 21 16 dpe sse rma rta 0 01 b dped 1 0 1 0 0 0 0 0 15 8 6 2 1 0 0 0 0 0 0 0 0 se 0 per 0 0 0 bm ms 0 peb 20256 e pef 20256 e register description data sheet 131 04.2001 rta received target abort this bit will be set whenever a transaction in which the munich256 acted as bus master was terminated with target abort. 0 no target abort detected. 1 transaction terminated with target abort. this bit will be cleared by writing a ?1? to this bit. dped data parity error detected 0 no data parity error detected. 1 the following three conditions are met: ? the bus agent asserted perr itself or observed perr asserted. ? the bus agent acted as bus master for the operation in which the error occurred. ? the parity error response bit is set se serr enable this bit enables assertion of serr in case of severe system errors. 0 assertion of serr disabled. 1 enables report of ? address parity errors ? master abort ? target abort per parity error response this bit enables reporting of parity errors via pin perr . 0 assertion of perr disabled. 1 enables the assertion of perr . see also data parity error detected. bm bus master this bit controls a device ability to act as a master on pci bus. 0 disables the device from generating pci accesses. 1 allows the device to act as bus master. ms memory space this bit controls the device response to memory space accesses. 0 response to memory space accesses disabled. 1 allows a device to respond to memory space accesses. peb 20256 e pef 20256 e register description data sheet 132 04.2001 cc/rid class code/revision id access : read address : 08 h reset value : 02800001 h the class code, consisting of base class, subsystem class and interface class, is used to identify the generic function of the device and, in some cases, a specific register-level programming interface. bcl base class the base class is hardwired to 02 h , which identifies this device as a network controller. scl sub class the sub class is hardwired to 80 h , which together with the base class identifies this device as ?other network controller?. icl interface class the interface class is hardwired to 00 h . rid revision id the revision id identifies the current version of the device. it is hardwired to 01 h . 31 24 23 16 bcl(7:0) scl(7:0) 15 8 7 0 icl(7:0) rid(7:0) peb 20256 e pef 20256 e register description data sheet 133 04.2001 bist/header type/latency timer/cache line size access : read/write address : 0c h reset value : 00000000 h lt latency timer the value of this register times eight specifies, in units of pci clocks, the value of the latency timer for this pci bus master. 31 24 23 16 00 h 00 h 15 11 10 8 7 0 lt(7:3) 000 b 00 h peb 20256 e pef 20256 e register description data sheet 134 04.2001 bar1 base address 1 access : read/write address : 10 h reset value : 00000000 h the first base address of the munich256 is marked as non-prefetchable and can be relocated anywhere in 32 bit address space of pci memory. the munich256 supports memory accesses only. bar base address the base address will be used for determining the address space of the munich256 and to do the mapping of the address space. since the device allocates a total of 4 kbyte address space bar(31:12) are implemented as read/writable. 31 16 bar(31:12) 15 12 2 1 0 bar(31:12) 0 0 0 0 0 0 0 0 0 00 b 0 peb 20256 e pef 20256 e register description data sheet 135 04.2001 bar2 base address 2 access : read/write address : 14 h reset value : 00000000 h the second base address of the munich256 is marked as non-prefetchable and can be relocated anywhere in 32 bit address space of pci memory. the munich256 supports memory accesses only. all accesses to memory regions defined by bar2 will be mapped to the local bus. bar base address the base address will be used for determining the address space of the memory regions located on the local bus of the munich256 and to set the mapping of the address space. the munich256 can access a total of 24 kbyte address space on the local bus as a bus master. in those applications where the master functionality of munich256 is not needed the second base address register bar2 may be disabled using bit mem.bar2 in the pci user configuration space. 31 16 bar(31:15) 15 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 b 0 peb 20256 e pef 20256 e register description data sheet 136 04.2001 sid/svid subsystem id/subsystem vendor id access : read address : 2c h reset value : 00000000 h sid subsystem id the subsystem id uniquely identifies the add-in board or subsystem where the system resides. the value of sid may be reconfigured after the reset phase of the system via the spi interface. svid subsystem vendor id the subsystem vendor id identifies the vendor of an add-in board or subsystem. the value may be reconfigured after the reset phase of the system via the spi interface. 31 16 sid(15:0) 15 0 svid(15:0) peb 20256 e pef 20256 e register description data sheet 137 04.2001 ml/mg/ip/il maximum latency/minimum grant/interrupt pin/interrupt line access : read/write address : 3c h reset value : 06020100 h ml maximum latency this value specifies how often the device needs to access the pci bus in multiples of 1/4 us. the value is hardwired to 06 h . mg minimum grant this value specifies how long of a burst period the device needs, assuming a clock rate of 33 mhz in multiples of 1/4 us. the value is hardwired to 02 h . ip interrupt pin the interrupt pin register tells which interrupt pin the device uses. refer to section 6.2.4 and to section 2.2.6 of the pci specification rev. 2.1. the value is hardwired to 01 h . il interrupt line the interrupt line register is used to communicate interrupt line routing information. 31 24 23 16 ml(7:0) mg(7:0) 15 8 7 0 ip(7:0) il(7:0) peb 20256 e pef 20256 e register description data sheet 138 04.2001 spi spi access register access : read/write address : 40 h reset value : 0000001f h spis spi start to start the eeprom transaction, which is defined in the spi command, the byte address, and the data field, this bit must be set to ?1? by a write transaction through the pci interface. after the transaction is finished, the start bit is deasserted by the spi interface controller. this signal must be polled by system software. scmd spi command in this register, the spi command for the next eeprom transfer must be written before the transaction is started. the following spi commands are supported: 01 h wrsr write status register 02 h write write data to memory array 03 h read read data from memory array 04 h wrdi reset write enable latch 05 h rdsr read status register 06 h wren set write enable latch sba spi byte address for read and write transaction to the connected eeprom, the byte address must be written in this register before the transaction is started. 31 24 23 16 0 0 0 0 0 0 0 spis scmd(7:0) 15 8 7 0 sba(7:0) swd(7:0) peb 20256 e pef 20256 e register description data sheet 139 04.2001 sd spi data for the write status register transactions and the write data to memory array transactions, the data, that has to be written to the eeprom, must be written to this register before the transaction is started. after a read status register transaction or read data from memory array transaction has finished (start bit is deasserted), the byte received from the eeprom is available in this register. peb 20256 e pef 20256 e register description data sheet 140 04.2001 lr long request register access : read/write address : 44 h reset value : 00000000 h lr long request 0 the pci interface deasserts the req signal in parallel with the assertion of the frame signal. 1 the req signal will be deasserted in parallel with the deassertion of frame . 31 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lr peb 20256 e pef 20256 e register description data sheet 141 04.2001 mem pci memory command register access : read/write address : 48 h reset value : 000007e6 h bar2 enable base address register 2 setting this bit enables base address register 2. per default base address register two is disabled. if an eeprom is connected to the spi interface the value of this bit can be loaded via the eeprom. additionally this bit can set using standard pci configuration write commands. 0 base address register 2 is disabled. 1 base address register 2 is enabled. mw memory write command the value of this register contains the write command to be used during initiator transfers and is set to memory write after reset. the value of this register is configurable during setup of the bridge either by loading the value from eeprom or by writing from pci side. mrl memory read command (long transfers) the value of this register defines command to be used for read transfers which are equal or more than two dwords and is set to memory read line after reset. the value of this register is configurable during run time of the bridge either by loading the value from eeprom or by writing from pci side. mr memory read command the value of this register defines command to be used for read transfers of single dwords.the value of this register is configurable during run 31 30 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bar2 0 15 11 8 7 4 3 0 0 0 0 0 mw(3:0) mrl(3:0) mr(3:0) peb 20256 e pef 20256 e register description data sheet 142 04.2001 time of the bridge either by loading the value from eeprom or by reading or writing from pci side. peb 20256 e pef 20256 e register description data sheet 143 04.2001 debug pci debug support register access : read address : 4c h reset value : 00000000 h dsr debug support register the value of this register contains the address of the next initiator transfer during normal operation. in case of disconnect, retry, master abort and target abort the register contains the address of the failed transaction. 31 16 dsr(31:0) 15 0 dsr(31:0) peb 20256 e pef 20256 e register description data sheet 144 04.2001 8.2.2 pci slave register cspec_cmd channel specification command register access : read/write address : 000 h reset value : 00000000 h the channel specification registers are the access registers to the chip internal channel database. in order to program or reprogram a channel the channel information must be setup in the channel specification data registers before a channel command can be given. as soon as the channel command is issued the channel information is copied to the chip internal channel database and the device is reconfigured for the intended operation. since reconfiguration time is dependent on the given command, certain commands generate acknowledge/fail command interrupt vectors to report status of configuration.during this time (command has been given and command interrupt) no further commands are allowed for the same channel. please note that any command for one channel does not affect operation of any other channel. for configuration of multiple channels the system software needs to program the channel data registers only once and then can issue channel commands for multiple channels without reprogramming the channel data registers. note: debugging of channel information using the commands ?receive debug? or ?transmit debug? requires new programming of channel data registers for further operation. for detailed description of register concept and command concept refer to chapter ? channel programming / reprogramming concept ? on page115 . 31 24 23 16 cmdx(7:0) cmdr(7:0) 15 7 0 0 0 0 0 0 0 0 0 chan(7:0) peb 20256 e pef 20256 e register description data sheet 145 04.2001 cmdx command transmit for detailed description of transmit commands and programming sequences refer to chapter6.2 . 01 h transmit init 02 h transmit off 04 h transmit abort/branch 08 h transmit hold reset 10 h transmit debug 20 h transmit idle 40 h transmit update cmdr command receive for detailed description of receive commands and programming sequences refer to chapter6.3 . 01 h receive init 02 h receive off 04 h receive abort/branch 08 h receive hold reset 10 h receive debug chan channel select 0..255 selects the channel to be programmed or debugged. note: transmit init for a channel must be programmed only after reset or after a transmit off command, i.e. two transmit init commands for the same channel are not allowed. peb 20256 e pef 20256 e register description data sheet 146 04.2001 cspec_mode_rec channel specification mode receive register access : read/write address : 004 h reset value : 00000000 h del del (delete) demap this bit enables demapping of the control character del (7f h ). t his bit is valid in ppp modes only. 0 disable demapping of control character del. 1 enable demapping of control character del. accmx extended accm in addition to the channel specification receive accm map the user can select four global user definable characters for character demapping in ppp modes. setting one or more of the bits accm(3) through accm(0) enables the corresponding character which can be found in register rec_accmx. 0 disable the selected character in rec_accmx for character demapping. 1 enable the corresponding character in register rec_accmx for character demapping. rflag receive flag used in transparent mode only. the rflag constitutes the flag that is filtered from the received bit stream if enabled via bit tff. 31 28 27 24 23 16 0 0 0 del accmx(3:0) rflag(7:0) 15 14 13 12 11 10 9 8 1 0 0 sfde tff inv tmp crcx crc 32 crc dis 0 0 0 0 0 0 pmd(1:0) peb 20256 e pef 20256 e register description data sheet 147 04.2001 sfde short/small frame drop enable this bit enables either the drop of short frames or the drop of small frames. this bit is valid in hldc and ppp modes only. 0 short frame drop. frames smaller than four bytes payload data (crc32) or smaller than two bytes payload data (crc16) are dropped. this function is not available if bit crcx is enabled. 1 small frame drop. frames (payload and crc) which are smaller or equal to conf3.minfl are dropped. tff tma flag this bit enabled flag extraction in tma mode and is available if non of the bits belonging to this channel is masked. 0 no flag extraction 1 enable flag extraction. the flag specified in rflag will be extracted from the received data stream. inv bit inversion when bit inversion is enabled incoming channel data is inverted before processed by the protocol machine. e.g. incoming octet 81 h will be recognized as idle flag in hdlc mode. 0 no bit inversion 1 bit inversion tmp transparent mode packing this bit enables the transparent mode packing and is valid in tma mode only. this feature is applicable if at least one bit in any time slot is masked. 0 incoming masked bits are substituted with ?1?. the non-used (masked) data bits are substituted by ?1?s. 1 if subchanneling is used in transparent mode (i.e. less than 8 bits of a time slot are used), the non-used (masked) data bits are discarded. crcx crc transfer this bit enables the capability to store the crc checksum of incoming data packets in system memory together with the payload data. 0 the crc checksum from the incoming data packet will be removed from the packet and not transferred to the shared memory. 1 the crc checksum together with the payload data is transferred to the shared memory. peb 20256 e pef 20256 e register description data sheet 148 04.2001 crc32 crc32 select this bit selects the generator polynomial in the receiver. the checksum of incoming data packets will be compared against crc16 or crc32. crc select is valid in hdlc and ppp modes only. 0 select crc16 checksum. 1 select crc32 checksum. crcdis crc check disable this bit disables crc check in hdlc and ppp protocol modes. 0 crc check is enabled. 1 crc check is disabled. pmd protocol machine mode these bit fields select the protocol machine mode in receive direction. 00 b select hdlc operation. 01 b select bit synchronous ppp. 10 b select byte synchronous ppp. 11 b select transparent mode. peb 20256 e pef 20256 e register description data sheet 149 04.2001 cspec_rec_accm channel specification receive accm map register access : read/write address : 008 h reset value : 00000000 h any of the given characters can be selected for character demapping. if a bit is set the corresponding character is expected to be mapped by the control esc character and is removed if received. these bits are valid in octet synchronous ppp modes only. note: if this register needs to be reprogrammed, it must be done before accessing the register cspec_mode_rec. 31 16 1f h 1e h 1d h 1c h 1b h 1a h 19 h 18 h 17 h 16 h 15 h 14 h 13 h 12 h 11 h 10 h 15 0 0f h 0e h 0d h 0c h 0b h 0a h 09 h 08 h 07 h 06 h 05 h 04 h 03 h 02 h 01 h 00 h peb 20256 e pef 20256 e register description data sheet 150 04.2001 cspec_mode_xmit channel specification mode transmit register access : read/write address : 014 h reset value : 00000000 h fnum flag number fnum denotes the number of flags send between two frames. the flag number can be updated during transmission with command ?transmit update?. 0 one flag is sent between two frames (shared flag). 1..255 fnum+1 flags are sent between two frames. tflag transparent flag only valid if transparent mode is selected and if fa is enabled. tflag constitutes the flag that is inserted into the transmit bit stream. iftf interframe time fill this bit determines the interframe time fill in hdlc and ppp modes. 0 interframe time fill is 7e h . 1 interframe time fill is ff h . fa flag adjustment only valid if transparent mode is selected. 0 the value ff h is sent in sent in all tma mode exception conditions. 1 the value specified in tflag is sent in all tma mode exception conditions (e.g. idle). this bit can be set only when none of the bits belonging to this channels is masked. 31 24 23 16 fnum(7:0) tflag(7:0) 15 13 12 11 9 8 7 4 3 1 0 iftf 0 fa inv tmp 0 crc 32 crc dis accmx(3:0) del 0 pmd(1:0) peb 20256 e pef 20256 e register description data sheet 151 04.2001 inv bit inversion if bit inversion is enabled outgoing channel data is inverted after processed by the protocol machine. e.g. a outgoing idle flag is transmitted as octet 81 h in hdlc mode. 0 disable bit inversion. 1 enable bit inversion. tmp transparent mode pack this bit enables the transparent mode packing and is valid in tma mode only. this feature is applicable if at least one bit in any time slot is masked. 0 if subchanneling is used outgoing masked bits of data octet are discarded and substituted with ?1?. 1 if subchanneling is used outgoing masked bits are sent as ?1?. the remaining bits of data are sent in the next time slot. crc32 crc 32 select this bit selects the generator polynomial in the transmitter. the checksum of outgoing data packets will be generated according to crc16 or crc32. crc32 select is valid in hdlc and ppp modes only. 0 select crc16 generation. 1 select crc32 generation. crcdis crc disable this bit enables generation and transmission of a crc checksum. crc disable is valid in hdlc and ppp modes only. 0 crc generation and transmission is disabled. 1 crc generation and transmission is enabled. accmx enable extended accm character the selected bits in bit field accmx denote the enabled characters in xmit_accmx. in addition to the channel specification transmit accm map the user can select four global user definable characters for character mapping in ppp modes. setting one or more of the bits accm(3) through accm(0) enables the corresponding character which can be found in register xmit_accmx. 0 disable the selected character in xmit_accmx for character mapping. 1 enable the corresponding character in register xmit_accmx for character mapping. peb 20256 e pef 20256 e register description data sheet 152 04.2001 del del (delete) map flag this bit enables mapping of the control character del (7f h ). t his bit is valid in ppp modes only. 0 disable mapping of del. 1 enable mapping of del. pmd protocol machine mode this bit field selects the protocol machine mode in transmit direction. 00 b select hdlc operation. 01 b select bit synchronous ppp. 10 b select byte synchronous ppp. 11 b select transparent mode. peb 20256 e pef 20256 e register description data sheet 153 04.2001 cspec_xmit_accm channel specification transmit accm map register access : read/write address : 018 h reset value : 00000000 h any of the given characters can be selected for character mapping. if a bit is set the corresponding character will be mapped by the control esc character. these bits are valid in octet synchronous ppp modes only. 31 16 1f h 1e h 1d h 1c h 1b h 1a h 19 h 18 h 17 h 16 h 15 h 14 h 13 h 12 h 11 h 10 h 15 0 0f h 0e h 0d h 0c h 0b h 0a h 09 h 08 h 07 h 06 h 05 h 04 h 03 h 02 h 01 h 00 h peb 20256 e pef 20256 e register description data sheet 154 04.2001 cspec_buffer channel specification buffer configuration register access : read/write address : 020 h reset value : 00200000 h tqueue transmit interrupt vector queue this bit field determines the interrupt queue where channel interrupts transmit will be stored. itbs individual transmit buffer size note: please note that the internal architecture is 32 bit wide. therefore each buffer location corresponds to four data octets. the transmit buffer size configures the number of internal transmit buffer locations for a particular channel. buffer locations will be allocated on command transmit init and released after command transmit off. note: the sum of transmit forward threshold and transmit refill threshold must be smaller than the internal buffer size. tbrtc transmit buffer refill threshold code note: please note that the internal architecture is 32 bit wide. therefore each buffer location corresponds to four data octets. tbrtc is a coding for the transmit refill threshold. please refer to table 8-4 for correspondence between code and threshold. the internal transmit buffer has a programmable number of buffer locations per channel. when the number of free locations reach es the transmit buffer refill threshold the internal transmit buffer requests new data from the data management unit. 31 29 28 16 tqueue(2:0) itbs(12:0) 15 12 11 8 6 4 3 0 tb ft c(3:0) tb rt c(3:0) 0 rqueue(2:0) rbtc(3:0) peb 20256 e pef 20256 e register description data sheet 155 04.2001 tbftc transmit buffer forward threshold code note: please note that the internal architecture is 32 bit wide. therefore each buffer location corresponds to four data octets. tbftc is a coding for the transmit buffer forward threshold. please refer to table 8-4 for correspondence between code and threshold. the transmit buffer forward threshold code determines the number of buffer locations which must be filled until the protocol machine starts transmission. nevertheless the transmit buffer forwards data packets to the protocol machine as soon as a whole packet or the end of a packet is stored in the transmit buffer. rqueue receive interrupt queue. this bit field determines the interrupt queue number where channel interrupts receive will be stored. rbtc receive buffer threshold code note: please note that the internal architecture is 32 bit wide. therefore each buffer location corresponds to four data octets. rbtc is a coding for the receive buffer threshold. please refer to table 8-4 for correspondence between code and threshold. the receive buffer threshold determines the maximum packet size in dwords which will be stored in the internal receive buffer for a specific channel. when the packet size reaches the receive buffer threshold or a packet has been completely received, the packet will be forwarded to system memory. table 8-4 threshold codings coding threshold in dwords rbtc tb rt c tb ft c tpbl 0000 b 1 x x x x 0001 b 4 x x x x 0010 b 8 x x x x 0011 b 12 x x x x 0100 b 16 x x x x 0101 b 24 x x x x 0110 b 32 x x x x 0111 b 40 x x x x 1000 b 48 x x x x peb 20256 e pef 20256 e register description data sheet 156 04.2001 1001 b 64 x x x x 1010 b 96 not valid x not valid 1011 b 128 x 1100 b 192 x 1101 b 256 x 1110 b 384 x 1111 b 512 x coding threshold in dwords rbtc tb rt c tb ft c tpbl peb 20256 e pef 20256 e register description data sheet 157 04.2001 cspec_frda channel specification frda register access : read/write address : 024 h reset value : 00000000 h frda first receive descriptor address this 30-bit pointer contains the start address of the first receive descriptor. the receive descriptor is read entirely after the first request of the receive buffer and stored in the on-chip channel database. therefore all information in the descriptor pointed to by frda must be valid when the data management unit branches to this descriptor. the user can specify a new first receive descriptor address using receive abort/branch command. in this case the first receive descriptor address (frda) is used as a pointer to a new linked list. see details on commands in section ? channel commands ? on page116 . 31 16 frda(31:2) 15 2 1 0 frda(31:2) 0 0 peb 20256 e pef 20256 e register description data sheet 158 04.2001 cspec_ftda channel specification ftda register access : read/write address : 028 h reset value : 00000000 h ftda first transmit descriptor address this 30-bit pointer contains the start address of the first transmit descriptor. the transmit descriptor is read entirely after the first request of the transmit buffer and stored in the on-chip channel database. therefore all information in the descriptor pointed to by ftda must be valid when the data management unit branches to this descriptor. the user can specify a new first transmit descriptor address using the ?transmit abort/branch? command. in this case the first transmit descriptor address (ftda) is used as a pointer to a new linked list. see details on commands in chapter6.2 . 31 16 ftda(31:2) 15 0 ftda(31:2) 0 0 peb 20256 e pef 20256 e register description data sheet 159 04.2001 cspec_imask channel specification interrupt vector mask register access : read/write address : 02c h reset value : 00000000 h for each channel or command related interrupt vector an interrupt vector generation mask is provided. generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. for description of interrupt concept and interrupt vectors see chapter4.7.1 . the following definition applies: 1 the device will not generate the corresponding interrupt vector, i.e. the interrupt vector is masked. 0 an interrupt condition results in generation of the corresponding interrupt vector. channel interrupt vector transmit tab mask ?transmit abort? htab mask ?hold caused transmit abort? ur mask ?transmit underrun? tfe mask ?transmit frame end? command interrupt vector transmit ttc mask ?transmit command complete? 31 30 28 23 22 16 0 tab 0 htab 0 0 0 0 ur tfe 0 0 0 0 0 tcc 15 14 13 12 11 10 9 8 7 6 5 3 2 0 0 rab rfe hrab mfl r fod crc ilen rfop sf iftc 0 sfd sd 0 rcc peb 20256 e pef 20256 e register description data sheet 160 04.2001 command interrupt vector receive rab mask ?receive abort? rfe mask ?receive frame end? hrab mask ?hold caused receive abort? mfl mask ?maximum frame length exceeded? rfod mask ?receive frame overflow dmu? crc mask ?crc error? ilen mask ?invalid length? rfop mask ?receive frame overflow? sf mask ?short frame detected? iftc mask ?interframe time-fill flag? and ?interframe time-fill idle? sfd mask ?short frame dropped? sd mask ?silent discard? rcc mask ?receive command complete? peb 20256 e pef 20256 e register description data sheet 161 04.2001 conf1 configuration register 1 access : read/write address : 040 h reset value : 820000f1 h iip initialization in progress (read only) after reset (hardware reset or software reset) the internal ram?s are self initialized by the munich256. during this time (approx. 250 m s) no other accesses to the device than reading register conf1 or fconf are allowed. this bit must be polled until it has been deasserted by the munich256. 0 self initialization has finished. 1 self initialization in progress. stop stop after reset the munich256 can be switched to ?fast initialization? mode. during stop mode internal ram?s will not be accesses by internal state machines. this mode is for test purposes only and allows writing or reading the internal ram?s. 0 device is in normal operation. this bit must be set to zero after chip initialization. see also ? mode initialization ? on page122 . 1 device is in ?fast initialization mode?. this function is used for test purposes only. srst software reset this bit issues a software reset to the munich256. during software reset all interfaces except pci interface are forced into their idle state. after software reset is set the munich256 starts its self initialization and 31 25 24 23 21 20 16 iip 0 0 0 0 0 stop srst 28/16 0 mfle mfl(12:0) 15 8 7 6 5 4 3 2 1 0 mfl(12:0) mbim pbim rbim rfim sfl rbm lbe 1 peb 20256 e pef 20256 e register description data sheet 162 04.2001 iip will be asserted. when iip is deasserted system software can reset srst to ?0? to start normal operation again. 0 normal operation 1 start software reset. 28/16 select 28/16-port mode this bit switches between the 28-port mode and the 16-port mode. 0 switch to 16-port mode. 1 switch to 28-port mode. mfle maximum frame length check enable 0 disable maximum frame length check. 1 enable maximum frame length check. mfl maximum frame length mfl defines the maximum length of incoming data packets. packets exceeding the specified length are reported in the status field of the receive descriptor and if selected in an additional channel interrupt. mbim mailbox interrupt vector mask this bit enables or disables mailbox system interrupt vectors generated by the mailbox. 0 enable interrupt vector. 1 disable interrupt vector. pbim pci bridge interrupt vector mask this bit enables or disables the ?pci access error? interrupt vector generated by the pci bridge. 0 enable interrupt vector. 1 disable interrupt vector. rbim receive buffer interrupt vector mask this bit enables or disables system interrupt vectors ?receive buffer queue early warning? and ?receive buffer action queue early warning? which are generated by the receive buffer. rbim is valid only if bit rbm is set. 0 enable interrupt vector. 1 disable interrupt vector. rfim receive buffer failed interrupt vector mask this bit enables or disables the ?receive buffer access failed? interrupt vector. 0 enable interrupt vector. peb 20256 e pef 20256 e register description data sheet 163 04.2001 1 disable interrupt vector. sfl short frame length this bit is a global parameter which defines the length of short frames for all channels. 0 short frame is defined as a frame containing less than 4 bytes (crc16) or less than 6 bytes (crc32). 1 short frame is defined as a frame containing less than 2 bytes (crc16) or less than 4 bytes (crc32). rbm receive buffer monitor this bit is provided to switch between two monitoring functions of the receive buffer. receive buffer monitor functions are available in register rbth and rbmon. 0 the minimum free pool count is captured in register rbth. 1 an interrupt is generated, if the free pool counter falls below the value programmed in register rbth. lbe little/big endian byte swap this bit enables the little or big endian mode, which affects the data structures pointed to by data pointer of receive or transmit descriptor in system memory. registers, interrupt vectors or descriptors are not affected by little/big endian byte swap. 0 switch data section to little endian mode. 1 switch data section to big endian mode. peb 20256 e pef 20256 e register description data sheet 164 04.2001 conf2 configuration register 2 access : read/write address : 044 h reset value : 00000000 h sysq system interrupt queue sysq sets up the interrupt queue where system interrupt vectors will be written to. one system interrupt queue can be selected for system interrupts. portq(2:0) port interrupt vector queue portq sets up the interrupt queue where port interrupt vectors will be written to. one interrupt queue can be selected for port interrupts. tbe test breakout enable this bit enables the test breakout function. the incoming signals of the port selected via lpid are switched to the test ports and the incoming signals on the test port replace the output signals of the selected port. setting tbe enables the selected port (tri-state no longer active) and has priority over functions selected in register pmr and priority over bit tcod . the port may be disabled using register ren and ten to disable internal processing while test function is active. 0 disable test function. 1 enable test function. tcod transmit clock out disable 31 30 28 27 26 24 23 22 21 20 16 0 sysq(2:0) 0 portq(2:0) 0 tbe tcod 00000 b 15 13 12 8 7 0 rcl 0 0 lpid(4:0) lcid(7:0) peb 20256 e pef 20256 e register description data sheet 165 04.2001 0 the incoming transmit clock of port zero is visible on pin tclko. this function is available when port zero is operated in unchannelized mode. 1 pin tclko is set to tri-state. rcl remote channel loop the remote channel loop switches incoming data of one channel to the outgoing bit stream of the same channel. the bit rate of the receiver and the transmitter must be the same. the channel to be looped can be selected using bit field lcid. one channel at a time can be looped. 0 disable remote channel loop. 1 enable remote channel loop. lpid port identifier this bit field selects the port which shall be switched to the test port. see also bit conf1.tbe. lcid loop channel identifier this bit field selects the channel which shall be looped through the internal loop buffer. peb 20256 e pef 20256 e register description data sheet 166 04.2001 conf3 configuration register 3 access : read/write address : 048 h reset value : 00090000 h tpbl transmit packet burst length this bit field is a coding for the maximum burst length on pci bus, when data management unit fetches transmit packets. please refer to table8- 4 " threshold codings " on page155 for correspondence between code and maximum burst length. minfl minimum frame length only valid for those channel which have bit cspec_mode_rec.sfde set. minfl sets the minimum frame length in bytes (payload bytes and crc bytes) for frames which will be forwarded to system memory. if enabled the receive buffer will drop frames which are smaller or equal to the programmed value minfl to avoid wasting of pci bandwidth in case of error conditions. the small frame check is disabled, if minfl is set to zero. note: since the receive packets will be dropped inside the receive buffer, the receive packet threshold cspec_buffer.rtc has to be greater than minfl/4 in order to work properly. 31 19 16 0 0 0 0 0 0 0 0 0 0 0 0 tpbl(3:0) 15 13 8 0 0 0 minfl(5:0) 0 0 0 0 0 0 0 0 peb 20256 e pef 20256 e register description data sheet 167 04.2001 rbaft receive buffer access failed interrupt threshold register access : read/write address : 04c h reset value : 00000000 h rbaft receive buffer access failed interrupt threshold this register sets the threshold for the ?receive buffer access failed? interrupt vector. 31 16 rbaft(31:0) 15 0 rbaft(31:0) peb 20256 e pef 20256 e register description data sheet 168 04.2001 sfdt small frame dropped interrupt threshold register access : read/write address : 050 h reset value : 00000000 h sfdit small frame dropped interrupt vector threshold the programmed threshold defines the threshold for the ?small frame dropped? interrupt vector. as soon as the internal number of dropped, small frames reaches the programmed value a channel interrupt vector with bit sfd set will be generated. the actual value of dropped frames can be read using register sfdc. the value is applied to all 256 channels. 31 16 sfdit(31:0) 15 0 sfdit(31:0) peb 20256 e pef 20256 e register description data sheet 169 04.2001 pmiar port mode indirect access register access : read/write address : 060 h reset value : 00000000 h note: this register is an indirect access register which must be programmed before accessing the register pmr. aip auto increment port this bit enables the auto increment function of bit field port. each read/ write access to register pmr increments port. this allows to program multiple, consecutive ports without accessing pmiar again. 0 disable auto increment function. 1 enable auto increment function. port port select this bit field selects the port number, which can be accessed via register pmr. 0..27 port number 31 23 0 0 0 0 0 0 0 0 aip 0 0 0 0 0 0 0 15 4 0 0 0 0 0 0 0 0 0 0 0 0 port(4:0) peb 20256 e pef 20256 e register description data sheet 170 04.2001 pmr port mode register access : read/write address : 064 h reset value : 0104c000 h note: effected port is selected via register pmiar. all settings in this register affect the selected port only. pcm select port mode this bit field selects the port mode. 0000 b t1 mode (1.544 mhz) 1000 b e1 mode (2.048 mhz) 1001 b 4.096 mhz mode (16-port mode only) 1010 b 8.192 mhz mode (16-port mode only) 1111 b unchannelized mode tbs transmit bit shift this bit field defines the position of the transmit bits relative to the external transmit synchronization pulse. see ? interface timing in 16- port mode ? on page108 for interface characteristics and table 8-12 for correspondence between programmed value and bit shift. rbs receive bit shift this bit field defines the position of the receive bits relative to the external receive synchronization pulse. see ? interface timing in 16- port mode ? on page108 for interface characteristics and table 8-12 for correspondence between programmed value and bit shift. 31 28 24 22 18 16 pcm(3:0) 0 0 0 tbs(2:0) 0 0 0 rbs(2:0) 15 14 13 12 11 10 9 8 7 6 5 0 rim tim rxf txr rsf tsf 0 0 rpl lpl 0 0 0 0 0 peb 20256 e pef 20256 e register description data sheet 171 04.2001 rim receive synchronization error interrupt vector mask this bit disables generation of the port interrupt vector receive. see ? port interrupts ? on page85 for description of interrupt vectors. 0 enable 1 disable tim transmit synchronization error interrupt vector mask this bit disables generation of the port interrupt vector transmit. see ? port interrupts ? on page85 for description of interrupt vectors. 0 enable 1 disable rxf receive data falling this bit selects the sample mode of incoming receive data. receive data is sampled on the rising or falling edge of the incoming receive clock. 0 sample receive data on rising edge of receive clock. 1 sample receive data on falling edge of receive clock. txr transmit data rising this bit selects the synchronization mode for transmit data. transmit data is updated on the rising or falling edge of the selected transmit clock. 0 transmit data is updated on the falling edge of the corresponding transmit clock. 1 transmit data is updated on the rising edge of the corresponding transmit clock. rsf receive synchronization pulse falling this bit selects the sample mode for incoming receive synchronization pulse. the receive synchronization pulse can be sampled on the rising or falling edge of the incoming receive clock. 0 sample receive synchronization pulse on the rising edge of the receive clock. 1 sample receive synchronization pulse on the falling edge of the receive clock. peb 20256 e pef 20256 e register description data sheet 172 04.2001 tsf transmit synchronization pulse falling this bit selects the sample mode for incoming transmit synchronization pulse. the transmit synchronization pulse can be sampled on the rising or falling edge of the selected transmit clock. 0 sample transmit synchronization pulse on the rising edge of the selected transmit clock. 1 sample transmit synchronization pulse on the falling edge of the selected transmit clock. rpl remote payload loop this bit enables the remote payload loop of the selected port. 0 disable remote payload loop. 1 enable remote payload loop. lpl local port loop this bit enables the local port loop on the selected port. when local loops are closed, the corresponding transmit clock and the synchronization pulse is switched to the receive port. note: the transmit bit shift (pmr.tbs) and the receive bit shift (pmr.rbs) of the selected port must be identical. 0 disable local port loop. 1 enable local port loop. table 8-12 bit shift programmed value bit shift 000 b -4 001 b -3 010 b -2 011 b -1 100 b 0 101 b 1 110 b 2 111 b 3 peb 20256 e pef 20256 e register description data sheet 173 04.2001 ren receive enable register access : read/write address : 068 h reset value : 00000000 h ren receive enable setting a bit in this bit field enables the receive function of the selected port. after reset all ports are disabled and thus all incoming receive data is discarded. while a port is disabled communication between port handler, time slot assigner and synchronization function is disabled. a port should be enabled if it is correctly configured using registers pmiar and pmr. 0 disable receive port. 1 enable receive port. 31 27 16 0 0 0 0 ren(27:0) 15 0 ren(27:0) peb 20256 e pef 20256 e register description data sheet 174 04.2001 ten transmit enable register access : read/write address : 06c h reset value : 00000000 h ten transmit enable this bit field enables the transmit function of the selected port. after reset all transmit ports are disabled and thus all td lines are set to tri-state. while a port is reset the communication between port handler, time slot assigner and synchronization function is disabled. after the port mode has been selected using register pmiar and pmr a transmit port can be enabled. 0 disable transmit port. 1 enable transmit port. bits which are masked in the time slot mask register are tri-stated. 31 27 16 0 0 0 0 ten(27:0) 15 0 ten(27:0) peb 20256 e pef 20256 e register description data sheet 175 04.2001 tsaia time slot assignment indirect access register access : read/write address : 070 h reset value : 00000000 h dir direction this bit select the direction for which programming is valid. 0 program time slots in receive direction. 1 program time slots in transmit direction. ait auto increment time slot this bit enables the auto increment function of bit field tsnum. each read/write access to register tsad increments tsnum. this allows to program multiple, consecutive time slots without accessing tsaia again. 0 disable auto increment function. 1 enable auto increment function. port port select this bit field selects the port number, which can be accessed via register tsaia. 0..27 port number 31 23 16 dir 0 0 0 0 0 0 0 ait 0 0 0 0 0 0 0 15 12 8 6 0 0 0 0 port(4:0) 0 tsnum(6:0) peb 20256 e pef 20256 e register description data sheet 176 04.2001 tsnum time slot number this bit field selects the time slots, which can be accessed via register tsaia. valid time slot numbers are: 0..23 t1, unchannelized 0..31 e1 0..63 4.096 mhz channelized 0..127 8.192 mhz channelized peb 20256 e pef 20256 e register description data sheet 177 04.2001 tsad time slot assignment data register access : read/write address : 074 h reset value : 02000000 h note: the time slot assignment data register assigns a channel and a mask to a specific port/time slot combination. the related port/time slot must be chosen by accessing tsaia. the time slot assignment has to be done before a specific channel is configured for operation. after operation the port/time slot assignment of a particular channel has to be set to inhibit. inhibit inhibit time slot this bit disabled processing of the selected port/time slot. 0 the time slot is enabled. 1 the time slot is disabled. in receive direction incoming octets are discarded. in transmit direction the octet of this time slot and port is tri-stated . tma1st tma first this bit marks the first time slot belonging to a tma superchannel for tma synchronization. receiver starts processing data on the marked time slot. in transmit direction data transmission is started on the marked time slot. if tma channel uses only one time slot this bit must be set. chan channel number this bit field selects the channel number which will be associated to the port and time slot which is selected in register tsaia. 31 25 24 0 0 0 0 0 0 inhi bit tma 1st 0 0 0 0 0 0 0 0 15 8 7 0 chan(7:0) mask(7:0) peb 20256 e pef 20256 e register description data sheet 178 04.2001 mask mask bits setting a bit in this bit field selects the corresponding bit in a time slot which is enabled for operation. 0 in receive direction the corresponding bit is discarded. in transmit direction the bit is tri-stated . 1 in receive direction the corresponding bit is forwarded to the protocol machine (via time slot assigner). in transmit direction data on the serial line is generated by the protocol machine. peb 20256 e pef 20256 e register description data sheet 179 04.2001 rec_accmx receive extended accm map register access : read/write address : 080 h reset value : 00000000 h this register is only used by channels operated in octet synchronous ppp mode. a character written to this register is mapped with a control escape sequence, if the corresponding enable flag is set in the corresponding bit cspec_mode_rec.accmx(3:0). 31 24 23 16 char3(7:0) char2(7:0) 15 8 7 0 char1(7:0) char0(7:0) peb 20256 e pef 20256 e register description data sheet 180 04.2001 rbafc receive buffer access failed counter register access : read address : 084 h reset value : 00000000 h rbafc receive buffer access failed counter the read value of this register defines the number of packets which have been discarded due to inaccessibility of the internal receive buffer. a read access resets the counter to zero. 31 16 rbafc(31:0) 15 0 rbafc(31:0) peb 20256 e pef 20256 e register description data sheet 181 04.2001 sfdia small frame dropped indirect access register access : read/write address : 088 h reset value : 00000000 h aic auto increment channel this bit enables the auto increment function of bit field chan. each read/write access to register sfd increments chan by two. this allows to read the status of multiple channels without accessing sfdia again. 0 disable auto increment function. 1 enable auto increment function. clr clear this bit enables the counter mode on reads to register sfdc. 0 read of register sfdc does not affect the small frame dropped counter. 1 after reading register sfdc the value of the small frame dropped counter will be reset to zero. chan channel number this bit field selects the channel, whose status can be read in register sfdc. 0..255 channel number 31 23 22 16 0 0 0 0 0 0 0 0 aic clr 0 0 0 0 0 0 15 7 0 0 0 0 0 0 0 0 0 chan(7:0) peb 20256 e pef 20256 e register description data sheet 182 04.2001 sfdc small frame dropped counter register access : read address : 08c h reset value : 00000000 h these both bit fields show the current value of the small frame dropped counter of the channel n and n+1 selected via sfdia.chan. dependent on bit field sfdia.clr the counter will be cleared after they are read. sfdc++ small frame dropped counter for channel n+1 the number of dropped, small frames of channel sfdia.chan+1. sfdc small frame dropped counter the number of dropped, small frames of channel sfdia.chan. 31 16 sfdc++(15:0) 15 0 sfdc(15:0) peb 20256 e pef 20256 e register description data sheet 183 04.2001 xmit_accmx transmit extended accm map access : read/write address : 090 h reset value : 00000000 h this register is only used by a channel in octet synchronous ppp mode. a character written to this register will be mapped with a control escape sequence, if the corresponding enable flag is set in the cspec_mode_xmit register (accmx(3:0)). 31 24 23 16 char3(7:0) char2(7:0) 15 8 7 0 char1(7:0) char0(7:0) peb 20256 e pef 20256 e register description data sheet 184 04.2001 rbmon receive buffer monitor indirect access register access : read address : 0b0 h reset value : 02000bff h rbaqc receive buffer action queue free count the value of this register determines the actual number of free actions inside the receive buffer. rbfpc receive buffer free pool count the value of this register determines the actual number of free buffer locations inside the receive buffer. after reset a total number of 3072 receive buffer locations, which equals 12kb receive buffer, is available. 31 25 16 0 0 0 0 0 0 rbaqc(9:0) 15 11 0 0 0 0 0 rbfpc(11:0) peb 20256 e pef 20256 e register description data sheet 185 04.2001 rbth receive buffer threshold register access : read/write address : 0b4 h reset value : 02000001 h rbaqth receive buffer action queue free pool threshold function of rbaqth is dependent on bit conf1.rbm. conf1.rbm = ?0?: the minimum value of rbmon.rbaqc, which occurred since the last reset or the last read of this register, is captures in here. conf1.rbm = ?1?: a ?receive buffer action queue early warning? interrupt will be generated, if the receive buffer action queue free pool drops below the value programmed in bit field rbaqth. the value to be programmed must be in the range of 000 h to 1ff h . rbth receive buffer free pool threshold function of rbth is dependent on conf1.rbm. conf1.rbm = ?0?: the minimum value of rbmon.rbfp, which occurred since the last reset or the last read of this register, is captured in here. conf1.rbm = ?1?: a ?receive buffer queue early warning? interrupt vector will be generated, if the receive buffer free pool drops below the value programmed in bit field rbth. 31 25 16 0 0 0 0 0 0 rbaqth(9:0) 15 11 0 0 0 0 0 rbth(11:0) peb 20256 e pef 20256 e register description data sheet 186 04.2001 iqia interrupt queue indirect access register access : read/write address : 0e0 h reset value : 00000000 h dbg debug this bit selects the debug mode of the interrupt controller. when debug is set, the actual values of interrupt queue base address, interrupt queue length and high priority interrupt queue mask of queue q are copied to register iqba, iql and iqmask. the value can be read with a following access to these registers. note: setting debug is only allowed, if neither siqba, siql and siqm are set. 0 no operation 1 enable debug mode. siqm set high priority interrupt queue mask this bit field enables setup of the high priority interrupt queue mask of queue q. the value to be programmed has to be configured via register iqmask prior to a write access to this bit. 0 no operation 1 set high priority mask. 31 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 dbg siqm siql siqba 15 3 0 0 0 0 0 0 0 0 0 0 0 0 0 q(3:0) peb 20256 e pef 20256 e register description data sheet 187 04.2001 siql set interrupt queue length this bit field enables setup of the interrupt queue length of queue q. the value to be programmed has to be configured via register iql prior to a write access to this bit. 0 no operation 1 set interrupt queue length. siqba set interrupt queue base address this bit field enables setup of the interrupt queue base address of queue q. the value to be programmed has to be configured via register iqba prior to a write access to this bit. 0 no operation 1 update interrupt queue base address with value programmed in register iqba. q interrupt queue number this bit field determines the interrupt queue number for which programming is valid. the first eight (0..7) interrupt queues are used for channel, port and system interrupt vectors, while the last interrupt queue (8) is used for command interrupt vectors. interrupt queue number seven is per default the high priority interrupt queue. system software may setup the interrupt queue high priority mask, the interrupt queue length and the interrupt queue base address simultaneously by setting siql, siqba and siqm. the command interrupt queue has a fixed length of two times 256 dwords, that is one dword for each interrupt vector. it is possible to setup the interrupt queue high priority mask, the interrupt queue length and the interrupt queue base address concurrently by setting siqba, siql and siqm to ?1?. note: programming of interrupt queue length or interrupt queue high priority mask is not valid for the command interrupt queue (interrupt queue 8). note: programming of interrupt queue high priority mask is not valid for the high priority interrupt queue (interrupt queue 7). 0..8 interrupt queue peb 20256 e pef 20256 e register description data sheet 188 04.2001 iqba interrupt queue base address register access : read/write address : 0e4 h reset value : 00000000 h iqba interrupt queue base address the interrupt queue base address register assign s a base address to the eight channel interrupt queues and the command interrupt queue. to set a new base address for a specific queue, system software must first program iqba. afterwards the value is released by selecting the associated queue via bit field iqia.q and setting of bit iqia.siqba. the interrupt queue base address has to be dword aligned. whenever the base address of a particular interrupt queue is modified, the next interrupt vector written to that queue is stored in the first location of the queue. 31 16 iqba(31:2) 15 2 1 0 iqba(31:2) 0 0 peb 20256 e pef 20256 e register description data sheet 189 04.2001 iql interrupt queue length register access : read/write address : 0e8 h reset value : 00000000 h iql interrupt queue length this bit field assigns a interrupt queue length to the eight channel interrupt queues. to set the interrupt queue length of a specific queue, system software must first program iql. afterwards the value is released by selecting the associated queue via bit field iqia.q and setting of bit iqia.siql. iql specifies the interrupt queue length l (number of dwords) in the shared memory with l=(iql+1)*16 (maximum of 4092 dwords). note: iql = 255 equals a queue length of 1 dword. whenever the length of a particular interrupt queue is modified, the next interrupt vector written to that queue is stored in the first location of the queue. 31 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 7 0 0 0 0 0 0 0 0 0 iql(7:0) peb 20256 e pef 20256 e register description data sheet 190 04.2001 iqmask interrupt queue high priority mask access : read/write address : 0ec h reset value : 00000000 h for a description of the interrupt concept and interrupt vectors see chapter4.7.1 . in normal operation each channel interrupt vector is written to the interrupt queue associated with a specific channel, that is interrupt queue 0 to 7. the interrupt queue mask provides the functionality to forward selected channel interrupts to the high priority interrupt queue, which is hardwired as queue 7.therefore a mask can be set for each of the interrupt queues, which specifies the channel interrupt vector to be forwarded to the high priority interrupt queue. to set the iqmask for interrupt queues 0 to 6, system software must first program iqmask. afterwards the mask is released by selecting the affected interrupt queue via bit field iqia.q and setting of bit siqm. those interrupt vectors which have an interrupt bit set, that is also masked in this high priority mask are forwarded to the high priority interrupt queue instead of the regular interrupt queue associated with a specific channel. if a channel interrupt vector has at least one interrupt bit set, that is also masked in the high priority mask, the interrupt vector will be forwarded to the high priority interrupt queue. in case that a channel interrupt vector has at least one bit set, that is not masked in the high priority mask, the interrupt vector is queued into the regular interrupt queue associated with the corresponding channel. 31 30 28 23 22 16 thi tab 0 htab 0 0 0 0 ur tfe 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 3 2 0 rhi rab rfe hrab mfl r f0d crc ilen rfop sf iftc 0 sfd sd 0 0 peb 20256 e pef 20256 e register description data sheet 191 04.2001 gista/giack interrupt status/interrupt acknowledge register access : read/write address : 0f0 h reset value : 00000000 h depending on the corresponding bits in register gmask, an interrupt indication in this register will be flagged at pin inta . if an interrupt bit is masked (set to ?1?) in register gmask, system software has to poll this register in order to get status information of the disabled interrupt bit. intof interrupt overflow this bit indicates that interrupt information has been lost due to overload conditions of the internal interrupt controller. this interrupt indicates a severe system problem. if this bit is set and intof is not masked in register gmask, the interrupt pin inta will be asserted. intof is cleared, when an ?1? is written to this bit. 0 no interrupt overflow. 1 interrupt overflow. the interrupt will be cleared by writing a ?1? to the corresponding bit. lbi local bus interrupt the munich256 supports bridging of interrupts from the local bus to the pci bus. in this application the pin lint is used as an input and as soon 31 17 16 intof 0 0 0 0 0 0 0 0 0 0 0 0 0 lbi if 15 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 q8 q7 q6 q5 q4 q3 q2 q1 q0 peb 20256 e pef 20256 e register description data sheet 192 04.2001 as lint changes from an inactive to an active state the interrupt pin inta will be asserted. note: this bit does not clear by writing a ?1?. this bit is set as long as the interrupt pin lint is asserted. 0 lint not asserted. 1 lint asserted. if interrupt fifo this bit indicates that there is an interrupt vector stored in the internal interrupt fifo. the if interrupt is available if the interrupt pin lint is switched to input mode (intctrl.id = ?1?) and when the interrupt mask gmask.if is set to ?0?. note: this bit does not clear by writing a ?1?. this bit is set as long as an interrupt vector is stored in the interrupt fifo. 0 no interrupt vector in interrupt fifo. 1 interrupt vector stored in internal interrupt fifo. q8..q0 interrupt queue 8..0 on reads each bit flags one or more interrupt vectors that have been written to the corresponding interrupt queue. if one of the bits is set and the same bit is not masked in register gmask, the interrupt pin inta will be asserted. a bit is cleared, when an ?1? is written to the specific bit. 0 no interrupt vector written. 1 read: one or more interrupt vectors have been written to interrupt queue. write: clear bit peb 20256 e pef 20256 e register description data sheet 193 04.2001 gmask global interrupt mask register access : read/write address : 0f4 h reset value : ffffffff h each bit in this register mask the interrupts, which are flagged in register gista/giack. intof mask interrupt overflow this bit masks the interrupt overflow interrupt. lint local bus interrupt this bit masks bridging of interrupt from the local bus to the pci bus. 0 bridging of lint to inta enabled. 1 bridging of lint to inta disabled. if interrupt fifo this bit masks the internal mailbox/layer one interrupt fifo. 0 if interrupt is enabled. 1 if interrupt is disabled. q8..q0 mask interrupt queue 8..0 each of the bits q8..q0 masks an interrupt, which will be asserted, when an interrupt vector has been written to the corresponding interrupt queue 8..0. masking an interrupt does not suppress generation of the interrupt vector itself. 0 enable interrupt, when interrupt vector has been written to selected interrupt queue. 1 mask (disable) interrupt, when interrupt vector has been written to selected interrupt queue. 31 17 16 intof 1 1 1 1 1 1 1 1 1 1 1 1 1 lint if 15 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 q8 q7 q6 q5 q4 q3 q2 q1 q0 peb 20256 e pef 20256 e register description data sheet 194 04.2001 8.8.1 pci and local bus slave register set fconf configuration register access : read/write address : 100 h (pci), 00 h (local bus) reset value : 8080 h iip initialization in progress (read only) after reset (hardware reset or software reset) the internal ram?s are self initialized by the munich256. during this time (approx. 250 m s) no other accesses to the device than reading register conf1 or fconf are allowed. this bit must be polled until it has been deasserted by the munich256. 0 self initialization has finished. 1 self initialization in progress. mbid mailbox interrupt vector disable 0 enable generation of mailbox interrupt vectors. as soon as system software on pci side writes to register mbp2e0 an interrupt vector indicating a mailbox interrupt will be forwarded to the internal interrupt fifo and can be read by the local cpu. 1 disable generation of mailbox interrupt vectors. wse wait state enable this bit enables the wait state controlled master mode. 0 lrdy (intel), ldtack (motorola) controlled bus mode. 1 wait state controlled bus mode. wait states are defined in register mtimer.ws. 15 14 7 6 5 4 3 2 1 0 iip 0 0 0 0 0 0 0 mbid wse bsd p28 p18 p08 lae lme peb 20256 e pef 20256 e register description data sheet 195 04.2001 bsd byte swap disable this bit disables byte swapping on 16-bit transfers when the local bus is operated in motorola master mode. 0 enable byte swap. 1 disable byte swap. p28..p08 switch page 2..0 to 8-bit mode the munich256 maps three pages of 8 kbyte each to the local bus in master mode. each page accessed from the pci side can be mapped in 8-bit mode or 16-bit mode. in 8-bit mode the data bits ld(15:8) are unused. 0 set page mode to 16-bit mode. 1 set page mode to 8-bit mode. lae local bus arbiter enable this bit enables the local bus arbiter. in case that the local bus arbiter is enabled the munich256 will arbitrate for each bus access on the local bus using the arbitration signals. if local bus arbiter functionality is disabled it assumes bus ownership and does not arbitrate for the local bus. 0 disable the local bus arbiter. 1 enable the local bus arbiter. lme local bus master enable this bit enables the local bus master functionality. as long as the local bus master functionality is disabled the munich256 can be accessed from the local bus as slave only. 0 disable local bus master. 1 enable local bus master. peb 20256 e pef 20256 e register description data sheet 196 04.2001 mtimer master local bus timer register access : read/write address : 104 h (pci), 02 h (local bus) reset value : 0000 h timer local bus latency timer timer*16 determines the time in clock cycles the munich256 holds the local bus as bus master after it was granted the bus. it holds the bus as long as the first transaction is in progress or the latency timer is counting. in case that the munich256 shall release the bus after it each transaction the latency timer value must be set to zero. ws wait state timer the value of this register determines the time in clock cycles the munich256 asserts lrd , lwr (intel mode) respectively lds (motorola bus mode). see also fconf.wse. 15 4 3 0 timer(15:4) ws(3:0) peb 20256 e pef 20256 e register description data sheet 197 04.2001 intctrl interrupt control register access : read/write address : 108 h (pci), 04 h (local bus) reset value : 0001 h id interrupt direction this pin determines the direction of the interrupt pin lint . 0 lint is output. 1 lint is input. ip interrupt polarity 0 lint is active low. 1 lint is active high. cliq clear interrupt queue setting this bit will clear the internal interrupt fifo. this effects mailbox interrupts to the local bus. 0 no action 1 clear interrupt fifo. im interrupt mask this bit masks assertion of the pin lint when interrupts are stored in the internal interrupt fifo. if the interrupt direction bit is set to output mode interrupt are flagged at interrupt pin lint . if the interrupt direction is set to input mode interrupts are flagged at pin inta . 0 enable assertion of interrupt pin lint . 1 disable assertion of interrupt pin lint . 15 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 id ip cliq im peb 20256 e pef 20256 e register description data sheet 198 04.2001 intfifo interrupt fifo access : read address : 10c h (pci), 06 h (local bus) reset value : ffff h iv interrupt vector after the munich256 asserted interrupt pin lint on the local bus side, this bit field contains an interrupt vector containing interrupt information. please refer to section ? mailbox interrupts to the local bus ? on page94 for a detailed description of interrupt vector contents. 15 0 iv(15:0) peb 20256 e pef 20256 e register description data sheet 199 04.2001 mbe2p0 mailbox local bus to pci command register access : read/write address : 140 h (pci), 20 h (local bus) reset value : 0000 h mb mailbox data register this register can be written and read from local bus side. from pci side this register should be used as read only in order to allow stable interprocessor communication. write access to this register results in mailbox interrupt vectors on local bus side to the internal interrupt fifo when fconf.mbid is set to ?0?. 15 0 mb(15:0) peb 20256 e pef 20256 e register description data sheet 200 04.2001 mbe2p1-7 mailbox local bus to pci data register 1-7 access : read/write address : 144 h -15c h (pci), 22 h -2e h (local bus) reset value : 0000 h mb mailbox data register this register can be written and read from local bus side. from pci side this register should be used as read only in order to allow stable interprocessor communication. 15 0 mb(15:0) peb 20256 e pef 20256 e register description data sheet 201 04.2001 mbp2e0 mailbox pci to local bus status register access : read/write address : 160 h (pci), 30 h (local bus) reset value : 0000 h mb mailbox status register this register can be written and read from pci side. from local bus side this register should be used as read only in order to allow stable interprocessor communication. write access to this register results in mailbox interrupt vectors to pci side when conf1.mbim is set to ?0?. 15 0 mb(15:0) peb 20256 e pef 20256 e register description data sheet 202 04.2001 mbp2e1-7 mailbox pci to local bus data register 1-7 access : read/write address : 164 h -17c h (pci), 32 h -3e h (local bus) reset value : 0000 h mb mailbox data register this register can be written and read from pci side. from local bus side this register should be used as read only in order to allow stable interprocessor communication. note - it is recommended to set this register to 00 after reset for normal operation. 15 0 mb(15:0) peb 20256 e pef 20256 e electrical characteristics data sheet 203 04.2001 9 electrical characteristics 9.1 important electrical requirements both v dd3 and v dd25 can take on any power-on sequence. within 50 milliseconds of power-up the voltages must be within their respective absolute voltage limits. at power- down, within 50 milliseconds of either voltage going outside its operational range, both voltages must be returned below 0.1v. 9.2 absolute maximum ratings table 9-1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 9.3 dc characteristics a) power supply pins table 9-2 dc characteristics parameter symbol limit values unit min max ambient temperature under bias peb 20256 e pef 20256 e t a 0 -40 70 85 c junction temperature under bias t j 125 c storage temperature t stg -65 125 c voltage on any pin with respect to ground v s -0.5 v dd3 +0.5 v parameter symbol limit values unit test condition min. max. core supply voltage v dd25 2.25 2.75 v i/o supply voltage v dd3 3.0 3.6 v peb 20256 e pef 20256 e electrical characteristics data sheet 204 04.2001 b) non-pci interface pins table 9-3 dc characteristics (non-pci interface pins) t a = -40 to 85 c, v dd3 = 3.3 v 0.3 v, v dd25 = 2.5 v 0.25 v, v ss = 0 v core supply current v dd25 operationa l i cc25 < 350 ma power down (no clocks) i ccpd25 < 2 ma i/o supply current v dd3 operationa l i cc3 < 200 ma inputs at v ss / v dd3 no output loads. power down (no clocks) i ccpd3 < 2 ma sum of input leakage current and output leakage current (outputs hi-z) i li i lo < 10 m a power dissipation p <3 w parameter symbol limit values unit test condition min. max. l-input voltage v il -0.4 0.8 v h-input voltage v ih 2.0 v dd3 +0.4 v l-output voltage v ol 0.45 v i ql = 2 ma h-output voltage v oh 2.4 v i qh = -400 m a parameter symbol limit values unit test condition min. max. peb 20256 e pef 20256 e electrical characteristics data sheet 205 04.2001 c) pci interface pins table 9-4 dc characteristics (pci interface pins) t a = -40 to 85 c, v dd3 = 3.3 v 0.3 v, v dd25 = 2.5 v 0.25 v, v ss = 0 v 9.4 ac characteristics a) non-pci interface pins t a = -40 to 85 c, v dd3 = 3.3 v 0.3 v, v dd25 = 2.5 v 0.25 v, v ss = 0 v inputs are driven to 2.4 v for a logical ?1? and to 0.4 v for a logical ?0?. timing measurements are made at 2.0 v for a logical ?1? and at 0.8 v for a logical ?0?. the ac testing input/output waveforms are shown below. ? figure 9-1 input/output waveform for ac tests b) pci interface pins pci interface pins are measured as pins compliant to the 3.3v signalling environment according to the pci specification rev. 2.1. parameter symbol limit values unit test condition min. max. l-input voltage v il -0.5 0.3 v dd3 - 80mv v h-input voltage v ih 0.5 v dd3 v dd3 +0.5 v l-output voltage v ol 0.1 v dd3 v i ql = 1500 m a h-output voltage v oh 0.9 v dd3 v i qh = -500 m a device under test 2.0 0.8 0.8 2.0 test points 0.45 2.4 c load = 50pf peb 20256 e pef 20256 e electrical characteristics data sheet 206 04.2001 9.4.1 pci bus interface timing ? figure 9-2 pci clock cycle timing table 9-5 pci clock characteristics note: rise and fall times are specified in terms of the edge rate measured in v/ns. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform shown in figure9-3 . ? figure 9-3 pci input timing measurement conditions parameter symbol limit values unit min. max. clk cycle time t cyc 15 ns clk high time t high 6 ns clk low time t low 7 ns clk slew rate (see note) 1.5 4 v/ns 0.2 v dd3 0.6 v dd3 0.5 v dd3 0.4 v dd3 0.3 v dd3 t high t low t cyc 0.4 v dd3 , p-to-p (minimum) t h input delay clock v test v test v tl v th t su v tl v th v test inputs valid v max peb 20256 e pef 20256 e electrical characteristics data sheet 207 04.2001 ? figure 9-4 pci output timing measurement conditions table 9-6 pci interface signal characteristics note: 1. minimum times are measured for 3.3v signalling environment according to the pci specification rev. 2.1. 2. req and gnt are point-to-point signals. all other signals are bussed. parameter symbol limit values unit notes min. max. clk to signal valid - bussed signals t val 2 8 ns 1, 2 clk to req valid t val 2 7 ns 1, 2 float to active delay t on 2 ns active to float delay t off 14 input setup time to clk - bussed signals t su 4 2 input setup time to clk - gnt t su 5 2 input hold time from clk t h 0.5 t off t on t val tri-state output output delay clock v test v test v test v test v tl v th peb 20256 e pef 20256 e electrical characteristics data sheet 208 04.2001 9.4.2 spi interface timing ? figure 9-5 spi interface timing table 9-7 spi interface timing ? note: 1 spi clock is related to pci clock where the spi frequency is 1/78 of the pci frequency. all timings for spi interface are calculated with a pci clock running at 33 mhz. no. parameter limit values unit notes min. max. 1 spcs low to spclk delay 500 ns 1 2 spclk to spcs delay 500 ns 3 spclk high time 500 ns 4 spclk low time 500 ns 5 spcs to spso delay 100 ns 6 spclk to spso delay 100 ns 7 spsi to spclk setup time 100 ns 8 spsi to spclk hold time 100 ns 5 4 6 3 7 8 1 2 spcs spclk spso spsi peb 20256 e pef 20256 e electrical characteristics data sheet 209 04.2001 9.4.3 local microprocessor interface timing 9.4.3.1 intel bus interface timing (slave mode) ? figure 9-6 intel read cycle timing (slave mode) ? figure 9-7 intel write cycle timing (slave mode) 22 la lcs0 lrd lrdy ld 20 24 25 27 28 26 23 21 29 32 22 20 24 25 30 31 26 23 21 32 la lcs0 lwr lrdy ld peb 20256 e pef 20256 e electrical characteristics data sheet 210 04.2001 table 9-8 intel bus interface timing no. parameter limit values unit min. max. 20 la to lrd , lwr setup time 20 ns 21 la to lrd , lwr hold time 0 ns 22 lcs0 to lrd , lwr setup time 20 ns 23 lcs0 to lrd , lwr hold time 0 ns 24 lcs0 low to lrdy active delay 20 ns 25 lrd , lwr high to lrdy high delay 20 ns 26 lcs0 high to lrdy float delay 20 ns 27 lrd low to ld active delay 20 ns 28 lrd high to ld float delay 20 ns 29 lrdy low to ld valid delay 20 ns 30 ld to lwr setup time 20 ns 31 ld to lwr hold time 0 ns 32 lrd , lwr minimum high time 20 ns peb 20256 e pef 20256 e electrical characteristics data sheet 211 04.2001 9.4.3.2 intel bus interface timing (master mode) ? figure 9-8 intel read cycle timing (master mode, lrdy controlled) ? figure 9-9 intel write cycle timing (master mode, lrdy controlled) la lcs2,1 lrd lrdy lbhe 62b 65 60b 61b 60a 61a 62a 63a 63b lclk 66 ld 67a 67b la lcs2,1 lwr lrdy ld lbhe 62b 65 69a 69b 60b 61b 60a 61a 62a 63a 63b lclk 66 peb 20256 e pef 20256 e electrical characteristics data sheet 212 04.2001 ? figure 9-10 intel read cycle timing (master mode, wait state controlled) ? figure 9-11 intel write cycle timing (master mode, wait state controlled) la lcs2,1 lrd lbhe 62b 60b 61b 60a 61a 62a 63a 63b lclk ld 68a 68b ws*t cyc la lcs2,1 lwr ld lbhe 62b 69a 69b 60b 61b 60a 61a 62a 63a 63b lclk ws*t cyc peb 20256 e pef 20256 e electrical characteristics data sheet 213 04.2001 ? figure 9-12 intel bus arbitration timing table 9-9 intel bus interface timing (master mode) note: t cyc is the clock period of the pci clock. no. parameter limit values unit min. max. 60a lclk to la active delay 0 10 ns 60b lclk to la float delay 0 10 ns 61a lclk to lcs2,1 active delay 0 10 ns 61b lclk to lcs2,1 float delay 0 10 ns 62a lclk to lbhe active delay 0 10 ns 62b lclk to lbhe float delay 0 10 ns 63a lclk to lrd , lwr active delay 0 10 ns 63b lclk to lrd , lwr float delay 0 10 ns 65 lrdy low to lrd , lwr high delay 2 t cyc 66 lrdy to lrd , lwr hold time 0 ns 67a ld to lrd s etup time 0 ns 67b ld to lrd h old time 0 ns 68a ld to lclk setup time 10 ns 68b ld to lclk hold time 0 ns 69a lclk to ld delay 0 10 ns 69b lclk to ld float delay 0 10 ns 70 lclk to lhold delay 0 10 ns 71 lhlda asserted to read/write cycle start 1 t cyc 72 lhlda minimum pulse width 2 t cyc lhold lhlda 70 lclk read/ write 71 72 peb 20256 e pef 20256 e electrical characteristics data sheet 214 04.2001 9.4.3.3 motorola bus interface timing (slave mode) ? figure 9-13 motorola read cycle timing (slave mode) ? figure 9-14 motorola write cycle timing (slave mode) 44 40 46 47 49 50 48 45 41 54 43 42 51 la lcs0 lrdwr ldtack ld lds 44 la lcs0 lrdwr ldtack ld 40 46 47 52 53 54 48 43 41 lds 42 45 peb 20256 e pef 20256 e electrical characteristics data sheet 215 04.2001 table 9-10 motorola bus interface timing no. parameter limit values unit min. max. 40 la to lds setup time 20 ns 41 la to lds hold time 0 ns 42 lcs0 to lds setup time 20 ns 43 lcs0 to lds hold time 0 ns 44 lrd wr to lds setup time 20 ns 45 lrd wr to lds hold time 0 ns 46 lcs0 low to ldtack active delay 20 ns 47 lds high to ldtack high delay 20 ns 48 lcs0 high to ldtack float delay 20 ns 49 lds low to ld active delay 20 ns 50 lds high to ld float delay 20 ns 51 ldtack low to ld valid delay 20 ns 52 ld to lds setup time 20 ns 53 ld to lds hold time 0 ns 54 lds minimum high time 20 ns peb 20256 e pef 20256 e electrical characteristics data sheet 216 04.2001 9.4.3.4 motorola bus interface timing (master mode) ? figure 9-15 motorola read cycle timing (master mode, ldtack controlled) ? figure 9-16 motorola write cycle timing (master mode, ldtack controlled) la lcs2,1 lds ldtack ld lsize0 82b 85 86 87a 87b 80b 81b lrdwr 83b 80a 81a 82a 83a 84a 84b lclk la lcs2,1 lds ldtack ld lsize0 82b 85 89a 89b 80b 81b lrdwr 83b 80a 81a 82a 83a 84a 84b lclk 86 peb 20256 e pef 20256 e electrical characteristics data sheet 217 04.2001 ? figure 9-17 motorola read cycle timing (master mode, wait state controlled) ? figure 9-18 motorola write cycle timing (master mode, wait state controlled) la lcs2,1 lds lsize0 82b 80b 81b lrdwr 83b 80a 81a 82a 83a 84a 84b lclk ld 88a 88b ws*t cyc la lcs2,1 lds ld lsize0 82b 89a 89b 80b 81b lrdwr 83b 80a 81a 82a 83a 84a 84b lclk ws*t cyc peb 20256 e pef 20256 e electrical characteristics data sheet 218 04.2001 ? figure 9-19 motorola bus arbitration timing table 9-11 motorola bus interface timing (master mode) no. parameter limit values unit min. max. 80a lclk to la active delay 0 10 ns 80b lclk to la float delay 0 10 ns 81a lclk to lcs2,1 active delay 0 10 ns 81b lclk to lcs2,1 float delay 0 10 ns 82a lclk to lsize0 active delay 0 10 ns 82b lclk to lsize0 float delay 0 10 ns 83a lclk to lrd wr active delay 0 10 ns 83b lclk to lrd wr float delay 0 10 ns 84a lclk to lds active delay 0 10 ns 84b lclk to lds float delay 0 10 ns 85 ldtack low to lds high delay 2 t cyc 86 ldtack to lds hold time 0 ns 87a ld to ldtack setup time 0 ns 87b ld to ldtack hold time 0 ns 88a ld to lclk setup time 10 ns 88b ld to lclk hold time 0 ns 89a lclk to ld delay 0 10 ns lbr lbg lbgack 93 90 92 lclk 94 read/ write 91 peb 20256 e pef 20256 e electrical characteristics data sheet 219 04.2001 note: t cyc is the clock period of the pci clock. note: status signals are generated synchronous to the pci clock. 89b lclk to ld float delay 0 10 ns 90 lclk to lbr delay 0 10 ns 91 lbgack to lbr delay 1 t cyc 92 lbg to lbgack hold time 0 ns 93 lbg to lbgack delay 1 t cyc 94 lclk to lbgack delay 0 10 ns no. parameter limit values unit min. max. peb 20256 e pef 20256 e electrical characteristics data sheet 220 04.2001 9.4.4 serial interface timing 9.4.4.1 clock input timing note: the clock input timings are calculated assuming pci clock frequency of 33 mhz or more. ? figure 9-20 clock input timing table 9-12 clock input timing no. parameter limit values unit min. max. unchannelized mode: high speed port 0 100 clock period 20 ns 101 clock high timing 7.5 ns 102 clock low timing 7.5 ns unchannelized mode: ports 1...27 100 clock period 100 ns 101 clock high timing 40 ns 102 clock low timing 40 ns e1, t1mode: all ports 100 clock period 480 ns 101 clock high timing 40 ns 102 clock low timing 40 ns all ports 103 clock fall time 10 ns 104 clock rise time 10 ns rclk(x) tclk(x) 100 101 102 103 104 peb 20256 e pef 20256 e electrical characteristics data sheet 221 04.2001 9.4.4.2 transmit cycle timing ? figure 9-21 transmit cycle timing note: 1. reference clock is only available in unchannelized mode for port zero. it is output on port tclko. 2. timing for transmit data which is updated on the rising edge of the transmit clock. 3. timing for transmit data which is updated on the falling edge of the transmit clock. table 9-13 transmit cycle timing no. parameter limit values unit min. max. unchannelized mode: high speed port 0 110 tclk(0) to tclko delay 15 ns 111 tclko to td(0) delay 0 5 ns 112 tclk(0) to td(0) delay 20 ns unchannelized mode: ports 1..15 e1, t1 mode: all ports 112 tclk(x) to td(x) delay 25 ns tclk(x) td(x) (note 2) td(x) (note 3) reference clock (note 1) 110 112 112 111 111 110 peb 20256 e pef 20256 e electrical characteristics data sheet 222 04.2001 9.4.4.3 transmit synchronization timing ? figure 9-22 transmit synchronization timing note: 1. timing for transmit synchronization pulse updated on the rising edge of the transmit clock. 2. timing for transmit synchronization pulse updated on the falling edge of the transmit clock. table 9-14 transmit synchronization timing no. parameter limit values unit min. max. e1, t1 mode: all ports 120 tsp(x) to tclk(x) setup time 5 ns 121 tsp(x) to tclk(x) hold time 5 ns tclk(x) (note 1) tsp(x) 120 121 tclk(x) (note 2) peb 20256 e pef 20256 e electrical characteristics data sheet 223 04.2001 9.4.4.4 receive cycle timing ? figure 9-23 receive cycle timing note: 1. timing for receive data sampled on the rising edge of the receive clock. 2. timing for receive data sampled on the falling edge of the receive clock. table 9-15 receive cycle timing no. parameter limit values unit min. max. e1, t1 mode: all ports 130 rd(x) to rclk(x) setup time 5 ns 131 rd(x) to rclk(x) hold time 5 ns rclk(x) (note 1) rd(x) 130 131 rclk(x) (note 2) peb 20256 e pef 20256 e electrical characteristics data sheet 224 04.2001 9.4.4.5 receive synchronization timing ? figure 9-24 receive synchronization timing note: 1. timing for receive synchronization pulse sampled on the rising edge of the receive clock. 2. timing for receive synchronization pulse sampled on the falling edge of the receive clock. table 9-16 receive synchronization timing no. parameter limit values min. max. e1, t1 mode: all ports 140 rsp(x) to rclk(x) setup time 5 141 rsp(x) to rclk(x) hold time 5 rclk(x) (note 1) rsp(x) 140 141 rclk(x) (note 2) peb 20256 e pef 20256 e electrical characteristics data sheet 225 04.2001 9.4.5 jtag interface timing ? figure 9-25 jtag interface timing table 9-17 jtag interface timing no. parameter limit values unit min. max. 200 tck period 120 ns 201 tck high time 60 ns 202 tck low time 60 ns 203 tms setup time 20 ns 204 tms hold time 20 ns 205 tdi setup time 20 ns 206 tdi hold time 20 ns 207 tdo valid time 50 ns trst tck tms tdi tdo 202 201 200 203 204 205 206 207 peb 20256 e pef 20256 e electrical characteristics data sheet 226 04.2001 9.4.6 reset timing ? figure 9-26 reset timing table 9-18 reset timing no. parameter limit values unit min. max. 220 rst pulse width 120 ns 221 number of clk cycles during rst active 2 clk cycles v dd3 clk 220 rst power-on 221 peb 20256 e pef 20256 e package outline data sheet 227 04.2001 10 package outline peb 20256 e pef 20256 e package outline data sheet 228 04.2001 peb 20256 e pef 20256 e list of abbreviations data sheet 229 04.2001 11 list of abbreviations abbreviation definition a/c analogue to digital adc analogue to digital converter ais alarm indication signal (blue alarm) agc automatic gain control alos analog loss of signa ami alternate mark inversion ansi american national standards institute atm asynchronous transfer mode sdh synchornous digital hierarchy sonet synchronous optical network esf extended superframe sf super frame hdlc high level data link control sdlc synchronous level data link control pci peripheral component interconnect. ds3 digital signal level 3 pll phase locked loop fdl facility data link spi serial peripheral interface bom bit oriented massage fifo first in first out auxp auxiliary pattern line 0 b8zs line coding to avoid too long strings of consecutive 0 ber bit error rate bfa basic frame alignment bom bit orientated message bellcore bell communications research bpv bipolar violation peb 20256 e pef 20256 e list of abbreviations data sheet 230 04.2001 bsn backward sequence number cas channel associated signaling cas-br channel associated signaling - bit robbing cas-cc channel associated signaling - common channel ccs common channel signaling cmi coded mark inversion (also known as 1t2b code) cr command/response (special bit in ppr) crc cyclic redundancy check csu channel service unit cvc code violation counter dco digitally controlled oscillator dl digital loop dpll digitally controlled phase locked loop ds1 digital signal level 1 ea extended address (special bit in ppr) prbs pseudo random binary sequence los loss of signal lof loss of frame wan wide area network dma direct memory access accm asynchronous control character map fcm frame check sum dword double word ( 4 bytes ) dmu data management unit abbreviation definition a/c analogue to digital peb 20256 e pef 20256 e list of abbreviations data sheet 231 04.2001 http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ?business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.? dr. ulrich schumacher |
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